公开(公告)号：US11417349B2

公开(公告)日：2022-08-16

申请号：US16803703

申请日：2020-02-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Peter John Frith ,  John Laurence Pennock

IPC: G06F17/00 ,  G10L19/16 ,  H04L25/49 ,  G10L19/002

Abstract: This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.

公开(公告)号：US10334339B2

公开(公告)日：2019-06-25

申请号：US15538584

申请日：2015-12-04

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Laurence Pennock ,  Tsjerk Hoekstra ,  David Talmage Patten

IPC: H04R19/00 ,  H04R1/04 ,  H04R1/28 ,  H04R19/04 ,  H04R31/00 ,  B81B7/00 ,  B81C1/00 ,  H04R1/34

Abstract: A MEMS transducer package (1) comprises a semiconductor die element (3) and a cap element (23). The semiconductor die element (3) and cap element (23) have mating surfaces (9, 21). The semiconductor die element (3) and cap element (23) are configured such that when the semiconductor die element (3) and cap element (4) are conjoined, a first volume (7, 27) is formed through the semiconductor die element (3) and into the semiconductor cap element (23), and an acoustic channel is formed to provide an opening between a non-mating surface (11) of the semiconductor die element (3) and a side surface (10, 12) of the transducer package.

公开(公告)号：US12002482B2

公开(公告)日：2024-06-04

申请号：US17845703

申请日：2022-06-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Peter John Frith ,  John Laurence Pennock

IPC: G06F17/00 ,  G10L19/002 ,  G10L19/008 ,  G10L19/16 ,  H04L25/49

CPC classification number: G10L19/167 ,  G10L19/002 ,  G10L19/008 ,  H04L25/49 ,  H04L25/4902 ,  H04L25/4904

Abstract: This application relates to methods and apparatus for transfer of multiple digital data streams, especially of digital audio data over a single communications link such as a single wire. The application describes audio interface circuitry comprising a pulse-length-modulation (PLM) modulator. The PLM is responsive to a plurality of data streams (PDM-R, PDM-L), to generate a series of data pulses (PLM) with a single data pulse having a rising and falling edge in each of a plurality of transfer periods defined by a first clock signal (TCLK). The timing of the rising and falling edge of each data pulse is dependent upon a combination of the then current data samples from the plurality of data streams. The duration and position of the data pulse in the transfer window in effect defines a data symbol encoding the data. Circuitry for receiving and extracting the data is also disclosed. An interface receives the stream of data pulses (PLM) and data extraction circuitry samples the data pulse to determine which of the possible data symbols the pulse represents and determines a data value for at least one received data stream.

公开(公告)号：US12184281B2

公开(公告)日：2024-12-31

申请号：US18478572

申请日：2023-09-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Laurence Pennock ,  John Paul Lesso

IPC: H03K19/0948 ,  H03K17/16 ,  H03K19/003 ,  H03M1/00

Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

公开(公告)号：US11604977B2

公开(公告)日：2023-03-14

申请号：US16859140

申请日：2020-04-27

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  John Laurence Pennock

IPC: G06N3/04 ,  G06N3/063 ,  G11C13/00

Abstract: This application relates to computing circuitry (200), in particular for analogue computing circuitry suitable for neuromorphic computing. The circuitry (200) has a plurality of memory cells (201), each memory cell having an input electrode (201) for receiving a cell input signal and an output (203P, 203N) for outputting a cell output signal (IP, IN), with first and second paths connecting the input electrode to the output. The cell output signal thus depends on a differential current between the first and second paths due to the cell input signal. Each memory cell also comprises at least one programmable-resistance memory element (204) in each of the first and second paths and is controllable, by selective programming of the programmable-resistance memory elements, to store a data digit that can take any of at least three different values. The plurality of memory cells are configured into one or more sets (205) of memory cells and a combiner module (206) receives the cell output signals from each of the memory cells in at least one set, and combines the cell output signals with a different scaling factor applied to each of the cell output signals.

公开(公告)号：US10187727B2

公开(公告)日：2019-01-22

申请号：US15659276

申请日：2017-07-25

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Robert David Rand ,  John Laurence Pennock

IPC: H04R5/02 ,  H04R5/04 ,  G06F13/38 ,  H01R13/66 ,  H01R29/00 ,  H04R1/10

Abstract: Embodiments of the present disclosure relate to methods and apparatus for peripheral device discovery, the detection of orientation of a connector having multiple degrees of rotational symmetry, and the provision of appropriate signal paths between a host device and a peripheral device. Some embodiments provide a characteristic impedance within the peripheral device that is coupled between rotationally symmetric contacts of the connector and thus enables detection of the connector orientation. The value of the characteristic impedance may be used in some embodiments to determine the type or model of peripheral device. Some embodiments are concerned with the enablement of appropriate signal paths to a peripheral device having a transducer (e.g. a loudspeaker) coupled only to rotationally symmetric contacts of the connector, such as headphones implemented in a “balanced” configuration.

公开(公告)号：US11223360B2

公开(公告)日：2022-01-11

申请号：US16934304

申请日：2020-07-21

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Laurence Pennock ,  John Paul Lesso

IPC: H03K19/0948 ,  H03K17/16 ,  H03K19/003 ,  H03M1/00

Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VRB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

公开(公告)号：US11831311B2

公开(公告)日：2023-11-28

申请号：US17536637

申请日：2021-11-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Laurence Pennock ,  John Paul Lesso

IPC: H03K19/0948 ,  H03K17/16 ,  H03K19/003 ,  H03M1/00

CPC classification number: H03K19/0948 ,  H03K17/161 ,  H03K19/00346 ,  H03K19/00369 ,  H03M1/001

Abstract: This application relates to control of semiconductor devices, in particular MOS devices, so as to reduce RTS/flicker noise. A circuit (100) includes a first MOS device (103, 104) and a bias controller (107). The circuit is operable in at least a first circuit state (PRO) in which the first MOS device is active to contribute to a first signal (Sout) and a second circuit state (PRST) in which the first MOS device does not contribute to the first signal. The bias controller is operable to control voltages at one or more terminals of the first MOS device to apply a pre-bias (VPB1, VPB2) during an instance of the second circuit state. The pre-bias is applied to set an occupancy state of charge carriers traps within the first MOS device, to limit noise during subsequent operation in the first circuit state. In embodiments, the bias controller is configured so that at least one parameter of the pre-bias is selectively variable in use based on one or more operating conditions.

公开(公告)号：US10691780B2

公开(公告)日：2020-06-23

申请号：US15667849

申请日：2017-08-03

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Sunil Saunders ,  Robert David Rand ,  Robert James Hatfield ,  John Laurence Pennock

IPC: G06F21/32 ,  H04W12/06 ,  H04L29/06 ,  G06F1/3231 ,  G06K9/00 ,  G06K9/62 ,  G10L17/22 ,  G06F3/16 ,  G06K9/68 ,  G10L17/02

Abstract: An electronic device, comprising one or more input devices, for receiving biometric input from a user and generating one or more biometric input signals; an applications processor; a mixer configurable by the applications processor to provide a first signal path between one or more of the input devices and the applications processor; and a biometric authentication module coupled to the one or more input devices via a second signal path that does not include the mixer, for performing authentication of at least one of the one or more biometric input signals.