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    SIGNAL TRANSMISSION AND RECEPTION SYSTEM, RECEPTION DEVICE, AND RECEPTION METHOD
    1.
    发明公开
    SIGNAL TRANSMISSION AND RECEPTION SYSTEM, RECEPTION DEVICE, AND RECEPTION METHOD 审中-公开

    公开(公告)号：US20240267267A1

    公开(公告)日：2024-08-08

    申请号：US18434966

    申请日：2024-02-07

    申请人： OLYMPUS MEDICAL SYSTEMS CORP.

    发明人： Shuichi Kato

    IPC分类号： H04L25/49 ,  H04L7/00

    CPC分类号： H04L25/4904 ,  H04L7/0066 ,  H04L7/0087

    摘要： A signal transmission and reception system includes a transmission device configured to transmit a transmission signal, a reception device configured to receive the transmission signal, in which the transmission device includes a Manchester coding circuit that generates an encoded signal in which transmission data is converted into a Manchester code as a switching edge, as at least a part of the transmission signal on the basis of a transmission clock, and the reception device includes a high-speed clock generation circuit, an edge detection circuit configured to detect an edge of the transmission signal, and a signal detection circuit configured to detect the edge detected in a period sandwiched between a first elapsed time at which a first period has elapsed from a start point and a second elapsed time at which a second period longer than the first period has elapsed from the start point as the switching edge.

    DYNAMIC SHIFT IN OUTPUTS OF SERIAL AND PARALLEL SCRAMBLERS AND DESCRAMBLERS
    2.
    发明公开
    DYNAMIC SHIFT IN OUTPUTS OF SERIAL AND PARALLEL SCRAMBLERS AND DESCRAMBLERS 审中-公开

    公开(公告)号：US20230344684A1

    公开(公告)日：2023-10-26

    申请号：US17727324

    申请日：2022-04-22

    申请人： Microsoft Technology Licensing, LLC

    发明人： Asaf LEVY

    IPC分类号： H04L25/03 ,  H04L25/49

    CPC分类号： H04L25/03872 ,  H04L25/4904 ,  H04L25/4902 ,  H04L2025/03356

    摘要： Methods, systems are provided for reconfiguring the position of a first tap in a descrambler circuit LFSR after the LFSR has been trained and synchronized with a corresponding scrambler circuit LFSR. A data path from the second tap position to the descrambler output by-passes logic elements located in the data path from the first tap to the descrambler output, thereby reducing delay in the descrambler circuit after the reconfiguration (i.e., the “lock-shift” operation). The tap position change may be communicated by a mode manager to a corresponding scrambler circuit, for applying a matching reconfiguration in the scrambler circuit, either directly via an I/O line or indirectly. The indirect route includes in-band transmissions between two ICs with two sets of self-synchronizing scrambler/descrambler pairs, and is based on monitored receiver LFSR output signals that indicate when a scrambler/descrambler pair is synchronized or whether the output of a descrambler circuit comprises descrambled data.

    IQ CLOCK PHASE CALIBRATION
    3.
    发明公开
    IQ CLOCK PHASE CALIBRATION 审中-公开

    公开(公告)号：US20230164010A1

    公开(公告)日：2023-05-25

    申请号：US17710983

    申请日：2022-03-31

    申请人： Shenzhen Goodix Technology Co., Ltd.

    发明人： Ahmed EMIRA ,  Mohamed ABOUDINA ,  Faisal HUSSIEN ,  Ayman Mohamed ELSAYED

    IPC分类号： H04L25/49

    CPC分类号： H04L25/4902 ,  H04L25/4904 ,  H04L25/4921

    摘要： A communication circuit is disclosed. The communication circuit includes a calibration system, configured to receive clock signals respectively having first and second clock phases, and first and second duty cycles, where the calibration system is further configured to receive input data and to adjust the input data to generate adjusted data based partly on the input data and based partly on the first and second duty cycles. The communication circuit also includes a mixer, configured to receive the clock signals and to receive the adjusted data, where the mixer is configured to generate output data based on the clock signals and the adjusted data, and where a mismatch in the output data caused by the first and second duty cycles being different is reduced because of the adjustment made to the input data to generate the adjusted data.

    EMBEDDED CLOCK IN A COMMUNICATION SYSTEM
    4.
    发明申请
    EMBEDDED CLOCK IN A COMMUNICATION SYSTEM 审中-公开

    公开(公告)号：US20190086947A1

    公开(公告)日：2019-03-21

    申请号：US16195275

    申请日：2018-11-19

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Robert Floyd Payne

    IPC分类号： G06F1/04 ,  H04L25/49 ,  H04B1/16 ,  H04B1/04

    CPC分类号： G06F1/04 ,  H04B1/04 ,  H04B1/16 ,  H04L25/4904 ,  H05K999/99

    摘要： Transmitter circuitry transmits: a first voltage as the return-to-zero signal that is higher than a first positive threshold, the first voltage being decodable to a first order of data bits; a second voltage as a return-to-zero signal that is between a second positive threshold and the first positive threshold, the second voltage being decodable to a second order of the data bits, and the second positive threshold being lower than the first positive threshold; a third voltage as the return-to-zero signal that is between a first negative threshold and a second negative threshold, the third voltage being decodable to a third order of the data bits, and the second negative threshold being higher than the first negative threshold; and a fourth voltage as the return-to-zero signal that is lower than the first negative threshold, the fourth voltage being decodable to a fourth order of the data bits. Clock circuitry transitions a clock signal for the return-to-zero signal crossing the second positive threshold, and for the return-to-zero signal crossing the second negative threshold.

    Communication system
    6.
    发明授权
    Communication system 有权
    通讯系统

    公开(公告)号：US09529771B2

    公开(公告)日：2016-12-27

    申请号：US12890122

    申请日：2010-09-24

    申请人： Christopher Paul Hulme Walker ,  Barry Michael Cook

    发明人： Christopher Paul Hulme Walker ,  Barry Michael Cook

    IPC分类号： H04L27/00 ,  G06F13/42 ,  H03M5/14 ,  H04L7/033 ,  H04L25/49 ,  H04L1/00 ,  H04L7/00 ,  H04L7/04

    CPC分类号： G06F13/4295 ,  H03M5/14 ,  H04L1/0002 ,  H04L7/0008 ,  H04L7/005 ,  H04L7/033 ,  H04L7/048 ,  H04L25/4904

    摘要： There is disclosed a method and apparatus for recovering data from a received signal, the received signal including a first signal comprising data bits and a second signal having transitions at data bit boundaries of the first signal where there is an absence of transitions, the method comprising: receiving the first signal; receiving the second signal; sampling the first signal to detect an edge transition of the first signal; sampling the second signal to detect an edge transition of the second signal; wherein on an active edge of either said first or said signal, the current value of the first signal is recovered as a received data bit.

    摘要翻译： 公开了一种用于从接收信号中恢复数据的方法和装置，所接收的信号包括包含数据位的第一信号和具有在不存在转换的第一信号的数据位边界处的转变的第二信号，该方法包括 ：接收第一个信号; 接收第二信号; 对第一信号进行采样以检测第一信号的边沿转换; 对第二信号进行采样以检测第二信号的边沿转变; 其中在所述第一或所述信号的有效边沿上，所述第一信号的当前值被恢复为接收数据位。

    METHOD AND APPARATUS FOR PROVIDING INPUT TO A CAMERA SERIAL INTERFACE TRANSMITTER
    7.
    发明申请
    METHOD AND APPARATUS FOR PROVIDING INPUT TO A CAMERA SERIAL INTERFACE TRANSMITTER 有权
    用于向摄像机串行接口发射器输入的方法和装置

    公开(公告)号：US20160212456A1

    公开(公告)日：2016-07-21

    申请号：US14598299

    申请日：2015-01-16

    申请人： ANALOG DEVICES GLOBAL

    发明人： Chris W. Bohm ,  Narsimh Dilip Kamath

    IPC分类号： H04N21/236 ,  B60R11/04 ,  H04N21/234 ,  H04N21/4223 ,  H04N21/2365 ,  H04N21/414 ,  H04H20/62

    CPC分类号： H04N21/23602 ,  B60R11/04 ,  G06F13/38 ,  G06F13/4291 ,  H04H20/62 ,  H04L1/0057 ,  H04L25/4904 ,  H04L25/493 ,  H04N7/18 ,  H04N7/181 ,  H04N21/23406 ,  H04N21/2365 ,  H04N21/41422 ,  H04N21/4223 ,  Y02D10/14 ,  Y02D10/151

    摘要： A system for receiving at least two data streams and providing a single input data stream to a MIPI's CSI Tx is disclosed. The two received data streams are written into respective data buffers. The system includes a control logic configured to control reading of data stored in the buffers to a multiplexer, the read-side clock being a multiple of a frequency of a fixed frequency clock. The control logic is further configured to control the multiplexer to combine data read from each buffer that corresponds to a complete unit of data into a separate portion and multiplex the separate portions into the input data stream. In this manner, two data streams may be transmitted using a single CSI Tx. When the two data streams are received by the system from an APIX interface, the system provides a bridge between the APIX interface and MIPI's CSI Tx.

    摘要翻译： 公开了一种用于接收至少两个数据流并向MIPI的CSI Tx提供单个输入数据流的系统。 两个接收的数据流被写入相应的数据缓冲器。 该系统包括控制逻辑，其被配置为控制将存储在缓冲器中的数据读取到多路复用器，读侧时钟是固定频率时钟频率的倍数。 控制逻辑还被配置为控制多路复用器将从与完整数据单元对应的每个缓冲器读取的数据组合成单独的部分，并将分离的部分复用到输入数据流中。 以这种方式，可以使用单个CSI Tx发送两个数据流。 当系统从APIX接口接收到两个数据流时，系统提供了APIX接口和MIPI的CSI Tx之间的桥梁。

    SERIALIZER AND DATA TRANSMITTER COMPRISING THE SAME
    8.
    发明申请
    SERIALIZER AND DATA TRANSMITTER COMPRISING THE SAME 有权
    串行数据发送器和数据发送器

    公开(公告)号：US20160173274A1

    公开(公告)日：2016-06-16

    申请号：US14965430

    申请日：2015-12-10

    申请人： Industry-Academic Cooperation Foundation, Yonsei University

    发明人： Woo-Young CHOI ,  Sung-Geun KIM

    IPC分类号： H04L7/06 ,  H04L7/08

    CPC分类号： H03M9/00 ,  H04L25/4904

    摘要： Disclosed is a serializer, which includes a data signal alignment unit aligning a plurality of data signals with a predetermined phase interval, a transition detection unit detecting a transition of a logic level among the aligned data signals to generate a toggle signal at a transition of the logic level, and a toggle signal conversion unit converting the toggle signal into a serial data signal obtained by serializing the data signals.

    摘要翻译： 公开了一种串行器，其包括以预定相位间隔对准多个数据信号的数据信号对准单元，转移检测单元检测对准的数据信号之间的逻辑电平的转变，以在转换中产生切换信号 逻辑电平和切换信号转换单元将切换信号转换为通过串行数据信号获得的串行数据信号。

    Device, system and method for bi-phase modulation decoding
    10.
    发明授权
    Device, system and method for bi-phase modulation decoding 有权
    用于双相调制解码的装置，系统和方法

    公开(公告)号：US09112763B1

    公开(公告)日：2015-08-18

    申请号：US14322103

    申请日：2014-07-02

    申请人： O2Micro Inc.

    发明人： Xiaogang Tan ,  Ke Gao ,  Fan Dou ,  Xinsheng Peng ,  James Wang

    IPC分类号： H04L25/49 ,  H04L27/233

    CPC分类号： H04L25/4904 ,  H02J7/025 ,  H02J50/00 ,  H02J50/15 ,  H02J50/80 ,  H03M13/3972 ,  H04L25/065 ,  H04L27/06

    摘要： The present disclosure discloses a device, system and method for bi-phase modulation decoding. The bi-phase modulation decoding device includes a sliding-window module and a determination module. The sliding-window module is configured to receive a baseband signal corresponding to a bi-phase modulated signal, and generate a filtered data packet by filtering the baseband signal using sliding-window digital filtering, wherein the filtered data packet comprises a series of sliding-window output values. The determination module configured to determine a bitstream corresponding to the bi-phase modulated signal based on the filtered data packet. The determination module determines a bit value of a first bit cycle of the bi-phase modulated signal based on a sign of a sliding-window output value of the first bit cycle and a sign of a sliding-window output value of a next bit cycle.

    摘要翻译： 本公开公开了一种用于双相位调制解码的装置，系统和方法。 双相位调制解码装置包括滑动窗口模块和确定模块。 滑动窗口模块被配置为接收对应于双相调制信号的基带信号，并且通过使用滑动窗口数字滤波对基带信号进行滤波来产生滤波后的数据分组，其中滤波的数据分组包括一系列滑动窗口模块， 窗口输出值。 所述确定模块被配置为基于所述经过滤的数据分组来确定与所述双相位调制信号相对应的比特流。 确定模块基于第一位周期的滑动窗口输出值的符号和下一个位周期的滑动窗口输出值的符号来确定双相调制信号的第一位周期的位值 。