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公开(公告)号：US11502671B2
公开(公告)日：2022-11-15
申请号：US17162950
申请日：2021-01-29
Inventor： Qiang Li , Rahul Singh , Paul Astrachan , Kyehyung Lee
Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.
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公开(公告)号：US20210044265A1
公开(公告)日：2021-02-11
申请号：US17002315
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier that includes a driver stage operable in a plurality of modes having different respective output impedances, a loop filter having an output, and a circuit configured to sense a current at a load of the Class-D amplifier, determine, based on the sensed current, an IR drop for a respective output impedance of the driver stage, and add the IR drop to the loop filter output to compensate for the respective output impedance of the driver stage to reduce distortion.
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公开(公告)号：US11290069B2
公开(公告)日：2022-03-29
申请号：US17002315
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier that includes a driver stage operable in a plurality of modes having different respective output impedances, a loop filter having an output, and a circuit configured to sense a current at a load of the Class-D amplifier, determine, based on the sensed current, an IR drop for a respective output impedance of the driver stage, and add the IR drop to the loop filter output to compensate for the respective output impedance of the driver stage to reduce distortion.
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Patent Agency Ranking
公开(公告)号：US20220247389A1
公开(公告)日：2022-08-04
申请号：US17162950
申请日：2021-01-29
Inventor： Qiang Li , Rahul Singh , Paul Astrachan , Kyehyung Lee
Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.
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公开(公告)号：US20210044264A1
公开(公告)日：2021-02-11
申请号：US17002270
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.
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公开(公告)号：US11245370B2
公开(公告)日：2022-02-08
申请号：US17002270
申请日：2020-08-25
Inventor： Zhaohui He , Ruoxin Jiang , Rahul Singh
Abstract: A Class-D amplifier includes a plurality of power rails, a quantizer, and a driver stage. The quantizer and the driver stage have a combined gain. For each power rail of the plurality of power rails, the Class-D amplifier senses a voltage value for the power rail and determines a ramp amplitude based on the sensed voltage value. The Class-D amplifier concurrently switches from the driver stage using a first power rail to a second power rail of the plurality of power rails and switches from the quantizer using the ramp amplitude associated with the first power rail to using the ramp amplitude associated with the second power rail so that the combined gain is constant.
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公开(公告)号：US10862442B2
公开(公告)日：2020-12-08
申请号：US16184909
申请日：2018-11-08
Inventor： Zhaohui He , Rahul Singh , Ruoxin Jiang
Abstract: In a Class-D amplifier, first/second ratios and first/second RC time constants are sequentially matched by trimming. An integrator is coupled to differential first/second paths. The first/second ratios are of a feedback resistor to an input resistor in the first/second paths. R's of the first/second RC time constants are the resistors of the first/second matched ratios. C's of the first/second RC time constants are integrating capacitors in the first/second path. For each of multiple power rails, a ramp amplitude is determined based on a sensed voltage. Concurrently, the driver stage is switched from first to second power rails and quantizer switched from first to second ramp amplitudes to achieve constant combined quantizer/driver stage gain. Based on a sensed load current, an IR drop is determined for a respective output impedance of the driver stage and added to a loop filter output to compensate for the respective output impedance.
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公开(公告)号：US10972061B2
公开(公告)日：2021-04-06
申请号：US16184511
申请日：2018-11-08
Inventor： Zhaohui He , Rahul Singh , Ruoxin Jiang
Abstract: A Class-D amplifier having a low power dissipation mode includes first and second independent output stages that receive respective first and second level power supply voltages for driving a load coupled to the amplifier output during respective first and second operating modes. Bypass switches are controllable to disconnect the second output stage from the output during the first operating mode and to connect the second output stage to the output during the second operating mode. The operating modes are selected based on the amplifier output power level. First and second independent pre-driver stages receive the respective first and second level power supply voltages for driving the respective first and second independent output stages. During the second operating mode the first pre-driver stage is placed into a low power dissipation state and during the first operating mode the second pre-driver stage is placed into a low power dissipation state.
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