公开(公告)号：US11502671B2

公开(公告)日：2022-11-15

申请号：US17162950

申请日：2021-01-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Qiang Li ,  Rahul Singh ,  Paul Astrachan ,  Kyehyung Lee

IPC: H03K3/017 ,  H04R3/00 ,  H03M3/00

Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

公开(公告)号：US20220247389A1

公开(公告)日：2022-08-04

申请号：US17162950

申请日：2021-01-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Qiang Li ,  Rahul Singh ,  Paul Astrachan ,  Kyehyung Lee

IPC: H03K3/017 ,  H03M3/00 ,  H04R3/00

Abstract: A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode.

公开(公告)号：US10476455B1

公开(公告)日：2019-11-12

申请号：US16057820

申请日：2018-08-08

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Inventor： Paul Astrachan ,  Emmanuel Marchais ,  Lingli Zhang ,  Zhaohui He ,  Kyehyung Lee ,  Tejasvi Das ,  John L. Melanson

IPC: H03F3/38 ,  H03F3/217 ,  H03M5/08 ,  H03K7/08

Abstract: A class-D amplifier system includes one or more pulse width modulation (PWM) output paths at least one of which includes one or more digital closed-loop PWM modulators (DCL-PWMM) in which at least one of the DCL_PWMM includes a digital integrator that provides an output value and receives a feedback value. The output value has an output resolution and the feedback value has a feedback resolution that is coarser than the output resolution. The output value is the sum of an integer multiple of the feedback resolution and a residue. Control logic decreases/increases the residue of the digital integrator toward an integer multiple of the feedback resolution over a plurality of clock cycles in response to a request to transition the class-D amplifier and forces an output of the DCL_PWMM to have an approximate 50% duty cycle after decreasing/increasing the residue over the plurality of clock cycles.