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1.发明申请公开(公告)号：US20180276550A1
公开(公告)日：2018-09-27
申请号：US15846538
申请日：2017-12-19
Applicant: D-Wave Systems Inc.
Inventor： Sheir Yarkoni , Kelly T.R. Boothby , Adam Douglass
Abstract: Quantum annealers as analog or quantum processors can find paths in problem graphs embedded in a hardware graph of the processor, for example finding valid paths, shortest paths or longest paths. A set of input, for example nucleic acid reads, can be used to set up a graph with edges between nodes denoting overlap (i.e., common base pairs) between the reads with constraints applied to perform sequence alignment or sequencing of a nucleic acid (e.g., DNA) strand or sequence, finding a solution that has a ground state energy. At least a portion of the described approaches can be applied to other problems, for instance resource allocations problems, e.g., job scheduling problems, traveling salesperson problems, and other NP-complete problems.
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公开(公告)号：US11138511B2
公开(公告)日：2021-10-05
申请号：US15846538
申请日：2017-12-19
Applicant: D-Wave Systems Inc.
Inventor： Sheir Yarkoni , Kelly T. R. Boothby , Adam Douglass
Abstract: Quantum annealers as analog or quantum processors can find paths in problem graphs embedded in a hardware graph of the processor, for example finding valid paths, shortest paths or longest paths. A set of input, for example nucleic acid reads, can be used to set up a graph with edges between nodes denoting overlap (i.e., common base pairs) between the reads with constraints applied to perform sequence alignment or sequencing of a nucleic acid (e.g., DNA) strand or sequence, finding a solution that has a ground state energy. At least a portion of the described approaches can be applied to other problems, for instance resource allocations problems, e.g., job scheduling problems, traveling salesperson problems, and other NP-complete problems.
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公开(公告)号：US20180246848A1
公开(公告)日：2018-08-30
申请号：US15549512
申请日：2016-01-27
Applicant: D-Wave Systems Inc.
Inventor： Adam Douglass , Richard G. Harris , Trevor Michael Lanting , Andrew Douglas King , Jack Raymond , Murray C. Thom
CPC classification number: G06F15/803 , G06N10/00
Abstract: A topology or hardware graph of a quantum processor is modifiable, for example prior to embedding of a problem, for instance by creating chains of qubits, where each chain which operates as a single or logical qubit to impose a logical graph on the quantum processor. A user interface (UI) allows a user to select a topology suited for embedding a particular problem or type of problem, to supply parameters that define the desired topology, or to supply or specify a problem graph or problem definition from which a processor-based system determines or selects an appropriate topology or logical graph to impose. Topologies may have regularity and/or self-similarity over the quantum processor or portions thereof, which portions may constitute unit cells. Logical graphs imposed on the quantum processor may take the form of a hypercube graph. A UI allows the user to specify a desired dimension of the hypercube graph.
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