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公开(公告)号：US20220020913A1
公开(公告)日：2022-01-20
申请号：US17330037
申请日：2021-05-25
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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公开(公告)号：US20210384406A1
公开(公告)日：2021-12-09
申请号：US17321819
申请日：2021-05-17
Applicant: D-WAVE SYSTEMS INC.
Inventor： Shuiyuan Huang , Byong H. Oh , Douglas P. Stadtler , Edward G. Sterpka , Paul I. Bunyk , Jed D. Whittaker , Fabio Altomare , Richard G. Harris , Colin C. Enderud , Loren J. Swenson , Nicolas C. Ladizinsky , Jason J. Yao , Eric G. Ladizinsky
IPC: H01L39/24 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/18 , H01L39/12
Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.
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公开(公告)号：US11182230B2
公开(公告)日：2021-11-23
申请号：US16702096
申请日：2019-12-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Richard G. Harris
IPC: G06F11/00
Abstract: Methods for reducing errors in calibrated devices comprise detecting outliers, self-checking consistency of measurements, tuning device controls to target values, and absolutely calibrating devices via a first standard and cross-checking the results via a second standard. The first standard may be a calibrated current and the second calibration standard may be a calibrated frequency. A calibrated frequency may be a microwave signal applied to the body of a qubit. Qubit annealing controls can quickly lower and raise the tunnel barrier to measures the oscillation frequency of the qubit between two potential wells.
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公开(公告)号：US20210013391A1
公开(公告)日：2021-01-14
申请号：US16098801
申请日：2017-05-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E.S. Johansson
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US20200183768A1
公开(公告)日：2020-06-11
申请号：US16702096
申请日：2019-12-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew J. Berkley , Richard G. Harris
Abstract: Methods for reducing errors in calibrated devices comprise detecting outliers, self-checking consistency of measurements, tuning device controls to target values, and absolutely calibrating devices via a first standard and cross-checking the results via a second standard. The first standard may be a calibrated current and the second calibration standard may be a calibrated frequency. A calibrated frequency may be a microwave signal applied to the body of a qubit. Qubit annealing controls can quickly lower and raise the tunnel barrier to measures the oscillation frequency of the qubit between two potential wells.
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Patent Agency Ranking
公开(公告)号：US20180246848A1
公开(公告)日：2018-08-30
申请号：US15549512
申请日：2016-01-27
Applicant: D-Wave Systems Inc.
Inventor： Adam Douglass , Richard G. Harris , Trevor Michael Lanting , Andrew Douglas King , Jack Raymond , Murray C. Thom
CPC classification number: G06F15/803 , G06N10/00
Abstract: A topology or hardware graph of a quantum processor is modifiable, for example prior to embedding of a problem, for instance by creating chains of qubits, where each chain which operates as a single or logical qubit to impose a logical graph on the quantum processor. A user interface (UI) allows a user to select a topology suited for embedding a particular problem or type of problem, to supply parameters that define the desired topology, or to supply or specify a problem graph or problem definition from which a processor-based system determines or selects an appropriate topology or logical graph to impose. Topologies may have regularity and/or self-similarity over the quantum processor or portions thereof, which portions may constitute unit cells. Logical graphs imposed on the quantum processor may take the form of a hypercube graph. A UI allows the user to specify a desired dimension of the hypercube graph.
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公开(公告)号：US20180218280A1
公开(公告)日：2018-08-02
申请号：US15881260
申请日：2018-01-26
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Kelly T.R. Boothby , Andrew D. King
CPC classification number: G06N10/00 , H01L39/00 , H01L39/223 , H01L49/006
Abstract: A system and method of operation embeds a three-dimensional structure in a topology of an analog processor, for example a quantum processor. The analog processor may include a plurality of qubits arranged in tiles or cells. A number of qubits and communicatively coupled as logical qubits, each logical qubit which span across a plurality of tiles or cells of the qubits. Communicatively coupling between qubits of any given logical qubit can be implemented via application or assignment of a first ferromagnetic coupling strength to each of a number of couplers that communicatively couple the respective qubits in the logical qubit. Other ferromagnetic coupling strengths can be applied or assigned to couplers that communicatively couple qubits that are not part of the logical qubit. The first ferromagnetic coupling strength may be substantially higher than the other ferromagnetic coupling strengths.
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公开(公告)号：US20170286859A1
公开(公告)日：2017-10-05
申请号：US15628963
申请日：2017-06-21
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Paul I. Bunyk , Mohammad H.S. Amin , Emile M. Hoskinson
Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
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公开(公告)号：US09607270B2
公开(公告)日：2017-03-28
申请号：US14846334
申请日：2015-09-04
Applicant: D-Wave Systems Inc.
Inventor： Richard G. Harris , Andrew J. Berkley , Jan Johansson , Mark Johnson , Mohammad Amin , Paul I. Bunyk
CPC classification number: H01L39/223 , B82Y10/00 , G06N99/002 , H01L27/18
Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
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公开(公告)号：US20160335558A1
公开(公告)日：2016-11-17
申请号：US14691268
申请日：2015-04-20
Applicant: D-Wave Systems Inc.
Inventor： Paul I. Bunyk , Mohammad H.S. Amin , Richard G. Harris , Trevor Michael Lanting , Mark W. Johnson , Jeremy P. Hilton , Emile M. Hoskinson
CPC classification number: G06N99/002 , G06F15/82
Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
Abstract translation: 在量子处理器中，一些耦合器将给定的量子比特耦合到最近的相邻量子位（例如，在有序2D阵列中垂直和水平），其他耦合器耦合到下一个最近的相邻量子位（例如，在有序2D阵列中的对角线）。 耦合器可以包括半耦合器，以选择性地提供给定量子位与其他量子位之间的通信耦合，其可以是也可以不是最近的，或者甚至不是最近邻近的。 可调谐耦合器选择性地介入交流耦合。 控制系统可以在量子处理器上施加不同于“被设计”或“制造”的物理连接的连接。 拼版可以通过数字处理器处理工作或更新的工作图，映射或嵌入问题图。 可以从硬件和工作图的比较中创建一组排除量子位。 退火计划可以调整一个或多个量子位的相应的归一化电感，例如排除某些量子位。
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