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公开(公告)号：US12046584B2
公开(公告)日：2024-07-23
申请号：US17861217
申请日：2022-07-10
IPC分类号： H01L23/538 , H01L23/00 , H01L23/498 , H01L25/07
CPC分类号： H01L25/072 , H01L23/49811 , H01L23/5386 , H01L24/49 , H01L2224/49175
摘要： A half bridge power module (1) comprising a substrate (2) comprising an inner load track (11), two intermediate load tracks (12, 14) and two outer load tracks (10,13), wherein an external terminal is mounted on one of the intermediate load tracks (12, 14), an external terminal (3, 4) is mounted on one of the outer load tracks (10, 13) and an external terminal (5) is mounted on the inner load track (11); wherein semiconductor switches (101, 12, 105, 106) are mounted on the outer load tracks (10, 13) and are electrically connected to the intermediate load track (12); and semiconductor switches (103, 104, 107, 108) are mounted on the intermediate load tracks (12, 14) and are electrically connected to the inner load track (11).
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公开(公告)号：US11532600B2
公开(公告)日：2022-12-20
申请号：US15931703
申请日：2020-05-14
IPC分类号： H01L23/538 , H01L23/495 , H01L25/07 , H01L23/00 , H01L23/498
摘要： A half bridge power module (1) comprising a substrate (2) comprising an inner load track (11), two intermediate load tracks (12, 14) and two outer load tracks (10,13), wherein an external terminal is mounted on one of the intermediate load tracks (12, 14), an external terminal (3, 4) is mounted on one of the outer load tracks (10, 13) and an external terminal (5) is mounted on the inner load track (11); wherein semiconductor switches (101, 12, 105, 106) are mounted on the outer load tracks (10, 13) and are electrically connected to the intermediate load track (12); and semiconductor switches (103, 104, 107, 108) are mounted on the intermediate load tracks (12, 14) and are electrically connected to the inner load track (11).
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公开(公告)号：US20220344310A1
公开(公告)日：2022-10-27
申请号：US17861217
申请日：2022-07-10
IPC分类号： H01L25/07 , H01L23/538 , H01L23/00 , H01L23/498
摘要： A half bridge power module (1) comprising a substrate (2) comprising an inner load track (11), two intermediate load tracks (12, 14) and two outer load tracks (10,13), wherein an external terminal is mounted on one of the intermediate load tracks (12, 14), an external terminal (3, 4) is mounted on one of the outer load tracks (10, 13) and an external terminal (5) is mounted on the inner load track (11); wherein semiconductor switches (101, 12, 105, 106) are mounted on the outer load tracks (10, 13) and are electrically connected to the intermediate load track (12); and semiconductor switches (103, 104, 107, 108) are mounted on the intermediate load tracks (12, 14) and are electrically connected to the inner load track (11).
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