公开(公告)号：US12130096B2

公开(公告)日：2024-10-29

申请号：US17753215

申请日：2020-08-28

申请人： JFE PRECISION CORPORATION ,  JFE STEEL CORPORATION

发明人： Hoshiaki Terao ,  Kouichi Hashimoto ,  Raita Wada

IPC分类号： F28F21/08 ,  H01L23/00 ,  H01L23/373 ,  B32B15/01 ,  H01L25/16

CPC分类号： F28F21/089 ,  H01L23/3735 ,  H01L24/32 ,  B32B15/018 ,  F28F2245/00 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32245 ,  H01L2224/48155 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/01042 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15763

摘要： Provided is a heat sink having a clad structure of Co—Mo composite materials and Cu materials, satisfying high heat-sink properties required of the heat sink for use in a semiconductor package with a frame on which a high-output and small-sized semiconductor is mounted, and preventing, when applied to the semiconductor package with a frame, crack of the frame due to local stress concentration. The heat sink has three or more Cu layers and two or more Cu—Mo composite layers alternately stacked in a thickness direction so that the Cu layers are outermost layers on both sides thereof, the Cu layers as the outermost layers each having a thickness t1 of 40 μm or more, the heat sink satisfying 0.06≤t1/T≤0.27 (where T: heat sink thickness) and t2/T≤0.36/[(total number of layers−1)/2] (where t2: Cu—Mo composite layer thickness, the total number of layers: sum of numbers of Cu layers and Cu—Mo composite layers).

公开(公告)号：US20240347499A1

公开(公告)日：2024-10-17

申请号：US18391942

申请日：2023-12-21

申请人： Samsung Electronics Co., Ltd.

发明人： Hongjin Kim

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/49 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45166 ,  H01L2224/45171 ,  H01L2224/4518 ,  H01L2224/45184 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49175 ,  H01L2224/49177 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

摘要： A semiconductor package includes a package substrate including a power pad and a ground pad that are spaced apart from each other in a first horizontal direction, first and second semiconductor chips on the package substrate, the first and second semiconductor chips being stacked in a stepped shape that extends in a second horizontal direction perpendicular to the first horizontal direction, and a plurality of connection wires that electrically connect the package substrate to the first semiconductor chip and/or the second semiconductor chip. The first semiconductor chip includes a plurality of lower option pads. The second semiconductor chip includes a plurality of upper option pads. The plurality of connection wires include a conductive wire that electrically connects at least one of first and second upper chip pads of the second semiconductor chip to at least one of the lower option pads of the first semiconductor chip.

公开(公告)号：US20240321813A1

公开(公告)日：2024-09-26

申请号：US18464738

申请日：2023-09-11

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

发明人： Syotaro ONO ,  Hisao ICHIJO ,  Hiroaki YAMASHITA

IPC分类号： H01L23/00 ,  H01L23/495

CPC分类号： H01L24/73 ,  H01L23/49513 ,  H01L24/05 ,  H01L24/32 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L23/49562 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/4005 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41051 ,  H01L2224/4805 ,  H01L2224/48245 ,  H01L2224/48476 ,  H01L2224/48499 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/10161 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device according to an embodiment includes: a die pad including an upper surface; a semiconductor chip provided on the upper surface, the semiconductor chip including a rectangular shape, and the semiconductor chip including an element region, and a termination region surrounding the element region; a first electrode provided on the semiconductor chip; a second electrode provided on the semiconductor chip; a first connector provided above the termination region, the first connector including a portion covering each of the four sides of the rectangular shape when viewed from above, and the first connector being electrically connected to the first electrode; and a sealing resin sealing a periphery of the semiconductor chip and the first connector.

公开(公告)号：US20240304510A1

公开(公告)日：2024-09-12

申请号：US18660967

申请日：2024-05-10

申请人： Rohm Co., Ltd.

发明人： Hiroaki MATSUBARA ,  Taro NISHIOKA ,  Yoshizo OSUMI

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/522 ,  H01L25/18

CPC分类号： H01L23/3135 ,  H01L23/291 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/5227 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/1815

摘要： A semiconductor device includes: a first semiconductor element; a second semiconductor element; an insulating element electrically connected to the first semiconductor element and the second semiconductor element, and insulating the first semiconductor element and the second semiconductor element from each other; and a sealing resin covering the first semiconductor element, the second semiconductor element, and the insulating element. The sealing resin includes a first portion covering the first semiconductor element, the second semiconductor element, and the insulating element, and a second portion constituting the outermost surface of the sealing resin. The second portion is less prone to a tracking phenomenon than the first portion.

公开(公告)号：US12087717B2

公开(公告)日：2024-09-10

申请号：US17369292

申请日：2021-07-07

申请人： Infineon Technologies Austria AG

发明人： Thomas Feil ,  Danny Clavette ,  Paul Ganitzer ,  Martin Poelzl ,  Carsten von Koblinski

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/07 ,  H01L25/16 ,  H01L27/088

CPC分类号： H01L24/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/072 ,  H01L25/16 ,  H01L27/088 ,  H01L23/3107 ,  H01L24/48 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06182 ,  H01L2224/08137 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/245 ,  H01L2224/2518 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73227 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/245 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/13055 ,  H01L2924/00

摘要： In an embodiment, a semiconductor package includes a first transistor device having first and second opposing surfaces, a first power electrode and a control electrode arranged on the first surface and a second power electrode arranged on the second surface. A first metallization structure arranged on the first surface includes a plurality of outer contact pads which includes a protective layer of solder, Ag or Sn. A second metallization structure is arranged on the second surface. A conductive connection extending from the first surface to the second surface electrically connects the second power electrode to an outer contact pad of the first metallization structure. A first epoxy layer arranged on side faces and on the first surface of the transistor device includes openings which define a lateral size of the plurality of outer contact pads and a package footprint.

公开(公告)号：US12080660B2

公开(公告)日：2024-09-03

申请号：US17228978

申请日：2021-04-13

申请人： CREE, INC.

发明人： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/00 ,  H01L25/07 ,  H01L29/16

CPC分类号： H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83121 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/29101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/29144 ,  H01L2924/0105 ,  H01L2224/29139 ,  H01L2924/0105 ,  H01L2224/29147 ,  H01L2924/0105 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012

摘要： A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

公开(公告)号：US20240282866A1

公开(公告)日：2024-08-22

申请号：US18568570

申请日：2022-06-09

申请人： Sumitomo Electric Device Innovations, Inc.

发明人： Kento KAWASAKI ,  Takuma MORI

IPC分类号： H01L29/94 ,  H01L23/00 ,  H01L25/18 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/94 ,  H01L24/05 ,  H01L24/06 ,  H01L25/18 ,  H01L29/417 ,  H01L29/66181 ,  H01L29/66196 ,  H01L24/03 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/03444 ,  H01L2224/03472 ,  H01L2224/05553 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49096 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/0132 ,  H01L2924/1205

摘要： The passive element includes a semiconductor substrate, a first insulating film, a first metal pad, a first conductor, and a first conductive film. The semiconductor substrate has p-type or n-type conductivity, and has a main surface and a back surface. The first insulating film is provided on a first region in the main surface of the semiconductor substrate. The first metal pad is provided on the first insulating film. The first conductor extends from the first metal pad in the first direction. The first conductive film is provided on a second region adjacent to the first region in a first direction in the main surface of the semiconductor substrate. The first conductive film is in ohmic contact with the main surface of the semiconductor substrate, and has an electrical resistivity lower than an electrical resistivity of the semiconductor substrate.

公开(公告)号：US20240282692A1

公开(公告)日：2024-08-22

申请号：US18652365

申请日：2024-05-01

申请人： Rohm Co., Ltd.

发明人： Yo MOCHIZUKI

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L25/07

CPC分类号： H01L23/49844 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49822 ,  H01L24/06 ,  H01L25/072 ,  H01L23/49811 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/37147 ,  H01L2224/40137 ,  H01L2224/40225 ,  H01L2224/40499 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/01047 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091

摘要： A semiconductor device includes a conductive member, a semiconductor element, and a sealing resin. The conductive member includes an obverse surface and a reverse surface facing away from each other in a thickness direction. The semiconductor element is bonded to the obverse surface. The sealing resin covers the conductive member and the semiconductor element. As viewed in the thickness direction, the obverse surface is surrounded by the reverse surface. The conductive member includes a first end surface located between the obverse surface and the reverse surface in the thickness direction. The first end surface is inclined relative to the reverse surface. The first end surface overlaps with the reverse surface as viewed in the thickness direction.

公开(公告)号：US12063030B2

公开(公告)日：2024-08-13

申请号：US18306707

申请日：2023-04-25

申请人： ROHM CO., LTD.

发明人： Masashi Hayashiguchi ,  Kazuhide Ino

IPC分类号： H02H3/00 ,  G01R19/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L25/07 ,  H01L25/18 ,  H02H3/20 ,  H02H9/04 ,  H02M7/5387 ,  H03K17/081 ,  H03K17/082 ,  H03K17/12 ,  H02M1/00

CPC分类号： H03K17/08104 ,  G01R19/0092 ,  H01L23/3107 ,  H01L23/3735 ,  H01L24/40 ,  H01L24/49 ,  H01L24/73 ,  H01L25/072 ,  H01L25/18 ,  H02H3/202 ,  H02H9/046 ,  H02M7/5387 ,  H03K17/0822 ,  H03K17/122 ,  H01L24/33 ,  H01L24/37 ,  H01L24/48 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H02M1/0009 ,  H03K2217/0027 ,  Y02B70/10 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2224/49175 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/49175 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/49111 ,  H01L2224/48247 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2224/83801 ,  H01L2924/00014

摘要： A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

公开(公告)号：US12051684B2

公开(公告)日：2024-07-30

申请号：US18241592

申请日：2023-09-01

申请人： Micron Technology, Inc.

发明人： Jong Sik Paek ,  Yeongbeom Ko

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498

CPC分类号： H01L25/18 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/50 ,  H01L23/49827 ,  H01L2224/02122 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207

摘要： Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.