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公开(公告)号：US08319509B1
公开(公告)日：2012-11-27
申请号：US13460006
申请日：2012-04-30
IPC分类号： G01R31/00
CPC分类号： H03M1/1071 , H03M1/12
摘要： A testing circuit configures an analog to digital converter (ADC) to receive a test signal instead of a live input signal. The testing circuit compares an output test value from the ADC to an expected test value for the test signal. The testing circuit provides an expected live output value to a digital circuit instead of the output test value, thereby preventing the ADC from providing a value to the digital circuit not based on the live input signal.
摘要翻译： 测试电路配置模数转换器（ADC）以接收测试信号而不是实时输入信号。 测试电路将ADC的输出测试值与测试信号的预期测试值进行比较。 测试电路为数字电路提供预期的实时输出值，而不是输出测试值，从而防止ADC根据实时输入信号为数字电路提供一个值。
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公开(公告)号：US20090201615A1
公开(公告)日：2009-08-13
申请号：US12030401
申请日：2008-02-13
IPC分类号： H02H9/04
CPC分类号： H02H9/046 , H01L2924/0002 , H02H1/04 , H01L2924/00
摘要： A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.
摘要翻译： 公开了一种使静电放电（ESD）保护电路的假触发最小化的技术。 在一个实施例中，ESD触发元件的电阻器 - 电容器（RC）时间常数在正常操作期间减小，从而最小化错误触发的风险。 保存电路布局区域，而不需要与释放保持触发状态的设备（即，触发锁存器）相关联的超时电路。 根据使用条件和ESD保护电路的期望应用，在操作上下文中设置用于触发的RC时间常数。
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公开(公告)号：US5783952A
公开(公告)日：1998-07-21
申请号：US714376
申请日：1996-09-16
CPC分类号： G11C27/028
摘要： A current cell for switch current circuits includes first and second MOS transistors connected in series between a constant current source and a reference ground. The first MOS transistor has its drain coupled to the constant current source and the second MOS transistor has its source coupled to the reference ground. Each of the two MOS transistors has a respective first and second switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current is applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor memorizes a gate voltage corresponding to the input current, constant current source current and a clock feedthrough error. A channel effect is purposely induced in the second MOS transistor to a degree sufficient to compensate for, and correct, its clock feedthrough error. A modulation voltage is induced at the drain of the second transistor as a result of the channel effect, and the first MOS transistor is used to store and maintain this modulation voltage at the drain of the second MOS transistor during the hold phase.
摘要翻译： 用于开关电流电路的电流单元包括串联连接在恒定电流源和参考地之间的第一和第二MOS晶体管。 第一MOS晶体管的漏极耦合到恒流源，第二MOS晶体管的源极耦合到参考地。 两个MOS晶体管中的每一个具有将其控制栅极耦合到其漏极的相应的第一和第二开关。 采样和保持操作的采样相分解为第一和第二采样子相，并且在两个采样子阶段期间将输入电流施加到当前单元。 在第一采样子相期间，第二MOS晶体管存储对应于输入电流，恒定电流源电流和时钟馈通误差的栅极电压。 通道效应在第二MOS晶体管中被故意地感应到足以补偿和校正其时钟馈通误差的程度。 作为沟道效应的结果，在第二晶体管的漏极处引起调制电压，并且在保持阶段期间，第一MOS晶体管用于在第二MOS晶体管的漏极处存储和维持该调制电压。
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公开(公告)号：US08009396B2
公开(公告)日：2011-08-30
申请号：US12030401
申请日：2008-02-13
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H01L2924/0002 , H02H1/04 , H01L2924/00
摘要： A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.
摘要翻译： 公开了一种使静电放电（ESD）保护电路的假触发最小化的技术。 在一个实施例中，ESD触发元件的电阻器 - 电容器（RC）时间常数在正常操作期间减小，从而最小化错误触发的风险。 保存电路布局区域，而不需要与释放保持触发状态的设备（即，触发锁存器）相关联的超时电路。 根据使用条件和ESD保护电路的期望应用，在操作上下文中设置用于触发的RC时间常数。
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