Abstract:
A computer system including a write protection circuit and a write poster is disclosed. The write protection circuit provides page description information to the computer system for controlling various operations. Illegal write operations as defined by the page description information are prevented from reaching a system bus and external cache. Internal cache invalidate operations may also be performed transparently to system operation. The write poster accepts write operations in zero wait states and assembles them into fewer more efficient writes to memory. A unique method and apparatus for programming a descriptor random access memory (RAM) is also provided.
Abstract:
An apparatus associated with a device connected to a data loop processes data received from the data loop to determine whether data from the data loop is to be routed back to the data loop. The apparatus may determine how to route data based on an analysis of whether the device is authorized to participate in a conversation currently associated with the data loop. Thus, latency otherwise imparted by the device when the device processes the data may be avoided.