公开(公告)号：US12130754B2

公开(公告)日：2024-10-29

申请号：US16995481

申请日：2020-08-17

申请人： Intel Corporation

发明人： Karthik Kumar ,  Francesc Guim Bernat

IPC分类号： G06F12/14 ,  G06F12/06 ,  G06F12/0813 ,  G06F12/0891

CPC分类号： G06F12/1441 ,  G06F12/0646 ,  G06F12/0813 ,  G06F12/0891 ,  G06F12/1483

摘要： Examples described herein relate to a network device apparatus that includes a packet processing circuitry configured to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, cause transmission of the memory access request to the different device. In some examples, the memory access request comprises an identifier of a requester of the memory access request and the identifier comprises a Process Address Space identifier (PASID) and wherein the configuration that a redirection operation is permitted to be performed for a memory access request is based at least on the identifier. In some examples, the packet processing circuitry is to: based on configuration of a redirection operation not to be performed for the memory access request, cause transmission of the memory access request to a device identified in the memory access request.

公开(公告)号：US12117942B2

公开(公告)日：2024-10-15

申请号：US18109675

申请日：2023-02-14

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics SA

发明人： Roberta Vittimani ,  Federico Goller ,  Riccardo Angrilli ,  Charles Aubenas

IPC分类号： G06F12/14

CPC分类号： G06F12/1441 ,  G06F12/1458

摘要： A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

公开(公告)号：US12061552B2

公开(公告)日：2024-08-13

申请号：US18315806

申请日：2023-05-11

申请人： Hewlett Packard Enterprise Development LP

发明人： Michael Malewicki ,  Thomas McGee ,  Michael S. Woodacre

IPC分类号： G06F12/08 ,  G06F12/0808 ,  G06F12/0817 ,  G06F12/084 ,  G06F12/14

CPC分类号： G06F12/0817 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/1441

摘要： Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

公开(公告)号：US12039090B2

公开(公告)日：2024-07-16

申请号：US17394014

申请日：2021-08-04

申请人： Cirrus Logic International Semiconductor Ltd.

发明人： Michael Chandler-Page ,  Pradeep Saminathan ,  Jon Eklund ,  Neil Whyte ,  José Arnaldo Bianco Filho ,  Abhinav Sharma

IPC分类号： G06F12/14 ,  G06F9/4401 ,  G06F13/16 ,  G06F21/71 ,  G06F21/60 ,  G06F21/62 ,  G06F21/74 ,  G06F21/76 ,  G06F21/85

CPC分类号： G06F21/71 ,  G06F9/4406 ,  G06F12/1441 ,  G06F13/1663 ,  G06F21/76 ,  G06F2212/1052

摘要： An integrated circuit comprises first and second interfaces, an internal addressable space comprising a plurality of address ranges, and a control unit. Each of the first and second interfaces is coupled to the internal addressable space via the control unit. The control unit is configurable in a first state in which the control unit is configured to allow or deny the second interface access to a subset of the plurality of address ranges of the internal addressable space.

公开(公告)号：US12019564B2

公开(公告)日：2024-06-25

申请号：US18098831

申请日：2023-01-19

申请人： Micron Technology, Inc.

发明人： Radhika Viswanathan ,  Bhumika Chhabra ,  Carla L. Christensen ,  Zahra Hosseinimakarem

IPC分类号： G06F12/14 ,  G06F21/31 ,  G06F21/79

CPC分类号： G06F12/1483 ,  G06F12/1441 ,  G06F21/31 ,  G06F21/79

摘要： Methods and apparatuses related to access to data stored in quarantined memory media are described. Memory systems can include multiple types of memory media (e.g., volatile and/or non-volatile) and data (e.g., information included in) stored in the memory media often are subject to risks of the data being undesirably exposed to the public. For example, requests to write data in the memory media can often be made and accepted without a user's awareness, which can lead to the undesirable exposure of the data. According to embodiments of the present disclosure, a particular portion and/or location in the memory media can provide a data protection scheme such that data stored in the particular location can be refrained from being transferred out of the computing system.

公开(公告)号：US20240143848A1

公开(公告)日：2024-05-02

申请号：US18189373

申请日：2023-03-24

申请人： Shanghai Zhaoxin Semiconductor Co., Ltd.

发明人： Zhenhua HUANG ,  Yingbing GUAN ,  Yanting LI

IPC分类号： G06F21/74 ,  G06F12/14 ,  G06F21/60

CPC分类号： G06F21/74 ,  G06F12/1441 ,  G06F21/604

摘要： A computing system with trusted computing is shown. The processor includes a normal core, and a trusted core for trusted computing. The system memory provides a normal memory, and an isolated memory for trusted computing. The chipset for the communication among the processor, the system memory, and peripherals includes a monitor and records memory protection configuration information. According to the memory protection configuration information, the monitor permits security peripherals to access the isolated memory, and prohibits normal peripherals from accessing the isolated memory.

公开(公告)号：US20240078191A1

公开(公告)日：2024-03-07

申请号：US18049683

申请日：2022-10-26

申请人： NXP B.V.

发明人： Vivek Singh ,  Nikhil Tiwari ,  Vishal Gulati

IPC分类号： G06F12/14

CPC分类号： G06F12/1441 ,  G06F12/1483 ,  G06F12/1491

摘要： An integrated circuit (IC), including a functional circuit and a security system, is disclosed. The functional circuit generates a request packet for an indirect memory access of a memory. The security system validates the functional circuit based on a security attribute and a functional identifier of the functional circuit. Based on the request packet and the validation of the functional circuit, the security system identifies an instruction sequence associated with the indirect memory access. Further, the security system determines a type of the indirect memory access based on the instruction sequence, and validates the type of the indirect memory access based on the security attribute and the request packet. Based on the validation of the type of the indirect memory access, the instruction sequence is executed, thereby facilitating the indirect memory access for the functional circuit.

公开(公告)号：US20240070090A1

公开(公告)日：2024-02-29

申请号：US18453108

申请日：2023-08-21

申请人： Apple Inc.

发明人： Jeff Gonion

IPC分类号： G06F12/14

CPC分类号： G06F12/1408 ,  G06F12/1441

摘要： In an embodiment, a system employs encryption on memory addresses generated by a source circuit that generates memory transactions (e.g., a processor such as a central processing unit (CPU), a graphics processing unit (GPU), various embedded processors or microcontrollers; or a peripheral device. The encrypted memory address corresponds to the row that is activated for the memory transaction, instead of the memory address generated by the source circuit.

公开(公告)号：US11914527B2

公开(公告)日：2024-02-27

申请号：US17452294

申请日：2021-10-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Bulent Abali ,  Alper Buyuktosunoglu

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F9/30 ,  G06F12/02

CPC分类号： G06F12/1441 ,  G06F9/30043 ,  G06F9/30047 ,  G06F12/0238

摘要： A first type memory and a second type memory may be identified in a computing system. The second type memory is slower than the first type memory while having a greater storage capacity compared to the first type memory. An application process executing in the computing system may be identified. A region of the first type memory may be provided as a cache of the second type memory for the application process.

公开(公告)号：US11907538B2

公开(公告)日：2024-02-20

申请号：US18045067

申请日：2022-10-07

申请人： Memory Technologies LLC

发明人： Jani Hyvonen ,  Kimmo J. Mylly ,  Jussi Hakkinen ,  Yevgen Gyl

IPC分类号： G06F3/06 ,  G06F13/16 ,  G11C7/20 ,  G06F12/14 ,  G06F12/06 ,  G06F13/28 ,  G06F21/79

CPC分类号： G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/1458 ,  G06F13/1694 ,  G06F13/28 ,  G11C7/20 ,  G06F12/1433 ,  G06F12/1441 ,  G06F21/79 ,  G06F2212/1052 ,  Y02D10/00

摘要： Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.