公开(公告)号：US5986955A

公开(公告)日：1999-11-16

申请号：US234268

申请日：1999-01-19

申请人： David D. Siek ,  Rajesh Somasekharan

发明人： David D. Siek ,  Rajesh Somasekharan

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1006

摘要： A hidden data path minimizes equilibration delays in coupling differential data through a complementary data path. The hidden data path may be used for both reading and writing to the memory cell array. The hidden data path includes two sets of complementary I/O lines coupled in parallel between the memory cell array and the DC sense amplifier, and are alternatively coupled between the memory cell array and the DC sense amplifier to receive and transmit data. The set of complementary I/O lines not coupled is equilibrated during this time in preparation for coupling to and transmitting subsequent differential data. The hidden data path may also include two sets of data read lines coupled in parallel between the DC sense amplifier and the output circuitry if used for reading data from the memory cell array. Similarly, a second set of data write lines may be coupled in parallel between the input circuitry and write driver circuit when used for writing data to the memory cell array.

摘要翻译： 隐藏的数据路径通过补充数据路径使差分数据的平衡延迟最小化。 隐藏的数据路径可以用于读取和写入存储器单元阵列。 隐藏数据路径包括并联在存储单元阵列和DC读出放大器之间的两组互补I / O线，并且交替耦合在存储单元阵列和DC读出放大器之间以接收和发送数据。 在此期间，不耦合的互补I / O线的平衡被准备用于耦合到并传送随后的差分数据。 如果用于从存储单元阵列读取数据，隐藏数据路径还可以包括并联在DC读出放大器和输出电路之间的两组数据读取线。 类似地，当用于将数据写入存储单元阵列时，第二组数据写入线可以并联连接在输入电路和写入驱动器电路之间。

公开(公告)号：US6040608A

公开(公告)日：2000-03-21

申请号：US964164

申请日：1997-11-04

申请人： Manny K. F. Ma ,  Rajesh Somasekharan ,  Wen Li

发明人： Manny K. F. Ma ,  Rajesh Somasekharan ,  Wen Li

IPC分类号： H01L29/10 ,  H01L29/68

CPC分类号： H01L29/1033 ,  Y10S257/901

摘要： A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

摘要翻译： 至少一个一次性可编程非易失性（NV）存储元件使用场效应晶体管（FET）作为选择性编程的元件。 施加漏电流的短时间超过FET的漏 - 源击穿电压导致漏源电阻基本上不受栅极端子施加的电压的影响。 由于编程电阻小于200欧姆，并且不需要高编程电压，因此本发明与反熔丝非易失性存储器技术相比是有利的。 实现非易失性存储元件，而不会增加对大规模集成（VLSI）电路过程的复杂性。

公开(公告)号：US5834813A

公开(公告)日：1998-11-10

申请号：US652376

申请日：1996-05-23

申请人： Manny K. F. Ma ,  Rajesh Somasekharan ,  Wen Li

发明人： Manny K. F. Ma ,  Rajesh Somasekharan ,  Wen Li

IPC分类号： H01L29/10 ,  H01L29/60

CPC分类号： H01L29/1033 ,  Y10S257/901

摘要： A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

公开(公告)号：US06828230B2

公开(公告)日：2004-12-07

申请号：US09388824

申请日：1999-09-01

申请人： Aaron Schoenfeld ,  Rajesh Somasekharan

发明人： Aaron Schoenfeld ,  Rajesh Somasekharan

IPC分类号： H01L2128

CPC分类号： H01L27/10885 ,  H01L21/76838 ,  H01L23/5283 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a substrate having a surface. A first conductive path is disposed on the substrate at a first level and has a first height. A second conductive path is also disposed on the substrate at the first level and has a second height that is significantly different than the first height. Where the integrated circuit is a memory circuit, the digit lines formed from a layer can have a smaller height than other signal lines that are formed from the same layer. Thus, the capacitive coupling between the digit lines can be reduced without degrading the current carrying capability of the other signal lines.

摘要翻译： 集成电路包括具有表面的基板。 第一导电路径设置在基底上的第一水平并具有第一高度。 第二导电路径也被设置在第一层的衬底上，并具有与第一高度显着不同的第二高度。 在集成电路是存储电路的地方，由层形成的数字线可以具有比由相同层形成的其它信号线更小的高度。 因此，可以减少数字线之间的电容耦合，而不降低其他信号线的电流承载能力。

公开(公告)号：US06396727B1

公开(公告)日：2002-05-28

申请号：US09505943

申请日：2000-02-15

申请人： Aaron Schoenfeld ,  Rajesh Somasekharan

发明人： Aaron Schoenfeld ,  Rajesh Somasekharan

IPC分类号： G11C502

CPC分类号： H01L27/10885 ,  H01L21/76838 ,  H01L23/5283 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a substrate having a surface. A first conductive path is disposed on the substrate at a first level and has a first height. A second conductive path is also disposed on the substrate at the first level and has a second height that is significantly different than the first height. Where the integrated circuit is a memory circuit, the digit lines formed from a layer can have a smaller height than other signal lines that are formed from the same layer. Thus, the capacitive coupling between the digit lines can be reduced without degrading the current carrying capability of the other signal lines.

摘要翻译： 集成电路包括具有表面的基板。 第一导电路径设置在基底上的第一水平并具有第一高度。 第二导电路径也被设置在第一层的衬底上，并具有与第一高度显着不同的第二高度。 在集成电路是存储电路的地方，由层形成的数字线可以具有比由相同层形成的其它信号线更小的高度。 因此，可以减少数字线之间的电容耦合，而不降低其他信号线的电流承载能力。