公开(公告)号：US20240363717A1

公开(公告)日：2024-10-31

申请号：US18771674

申请日：2024-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shahaji B. More ,  Chandrashekhar Prakash Savant

IPC分类号： H01L29/49 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/4916 ,  H01L29/1033 ,  H01L29/66545

摘要： In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.

公开(公告)号：US20240313050A1

公开(公告)日：2024-09-19

申请号：US18673998

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturering Co.,Ltd.

发明人： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC分类号： H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0673 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device includes nanosheets between the source/drain regions, and a gate structure over the substrate and between the source/drain regions, the gate structure including a gate dielectric material around each of the nanosheets, a work function material around the gate dielectric material, a first capping material around the work function material, a second capping material around the first capping material, wherein the second capping material is thicker at a first location between the nanosheets than at a second location along a sidewall of the nanosheets, and a gate fill material over the second capping material.

公开(公告)号：US12087839B2

公开(公告)日：2024-09-10

申请号：US18299438

申请日：2023-04-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shahaji B. More ,  Chandrashekhar Prakash Savant

IPC分类号： H01L29/49 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/4916 ,  H01L29/1033 ,  H01L29/66545

摘要： In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.

公开(公告)号：US12057487B2

公开(公告)日：2024-08-06

申请号：US18357761

申请日：2023-07-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Jhon Jhy Liaw

IPC分类号： H01L29/423 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51 ,  H10B10/00

CPC分类号： H01L29/42392 ,  H01L27/0207 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H10B10/12 ,  H10B10/18

摘要： An exemplary semiconductor memory chip includes a first static random access memory (SRAM) cell and a second SRAM cell. The first SRAM cell has a first GAA transistor, and the second SRAM cell has a second GAA transistor. The first and the second SRAM cells have a same cell size, and the first and the second GAA transistors are of a same transistor type. Moreover, the first GAA transistor has a first threshold voltage and the second GAA transistor has a second threshold voltage. The second threshold voltage is different than the first threshold voltage. Furthermore, the first GAA transistor has a first gate stack and the second GAA transistor has a second gate stack. The first gate stack has a first work function value, and the second gate stack has a second work function value. The second work function value is different than the first work function value.

公开(公告)号：US12057475B2

公开(公告)日：2024-08-06

申请号：US17471280

申请日：2021-09-10

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： HsinFu Lin ,  Tsung-Hao Yeh ,  Shiang-Hung Huang

IPC分类号： H01L29/06 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0653 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/1033

摘要： A field effect transistor contains a semiconductor material layer including a source-side doped well, a source region, and a drain region. A shallow trench isolation structure is embedded in the semiconductor material layer and extends between the source region and the drain region. Agate dielectric layer overlies the semiconductor material layer. A horizontally-extending portion of a gate electrode overlies the gate dielectric layer, and at least one downward-protruding portion of the gate electrode extends downward from a bottom surface of the horizontally-extending portion into an upper region of the shallow trench isolation structure. The gate electrode is vertically spaced from a bottom surface of the shallow trench isolation structure modifies electrical field in a semiconductor channel to reduce hot carrier injection.

公开(公告)号：US20240250141A1

公开(公告)日：2024-07-25

申请号：US18588727

申请日：2024-02-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

IPC分类号： H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66545

摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

公开(公告)号：US12048162B2

公开(公告)日：2024-07-23

申请号：US18102917

申请日：2023-01-30

申请人： LONGITUDE FLASH MEMORY SOLUTIONS LTD.

发明人： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC分类号： H10B43/30 ,  B82Y10/00 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/105 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/792 ,  H10B43/27 ,  H10B43/40 ,  H10B99/00

CPC分类号： H10B43/30 ,  B82Y10/00 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/105 ,  H01L29/1033 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/4925 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B43/27 ,  H10B43/40 ,  H10B99/00

摘要： An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

公开(公告)号：US12046634B2

公开(公告)日：2024-07-23

申请号：US18158148

申请日：2023-01-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Cheng-Wei Chang ,  Shuen-Shin Liang ,  Sung-Li Wang ,  Hsu-Kai Chang ,  Chia-Hung Chu ,  Chien-Shun Liao ,  Yi-Ying Liu

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/0665 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742

摘要： A semiconductor device with dual side source/drain (S/D) contact structures and methods of fabricating the same are disclosed. The semiconductor device includes first and second S/D regions, a nanostructured channel region disposed between the first and second S/D regions, a gate structure surrounding the nanostructured channel region, first and second contact structures disposed on first surfaces of the first and second S/D regions, a third contact structure disposed on a second surface of the first S/D region, and an etch stop layer disposed on a second surface of the second S/D region. The third contact structure includes a metal silicide layer, a silicide nitride layer disposed on the metal silicide layer, and a conductive layer disposed on the silicide nitride layer.

公开(公告)号：US20240222297A1

公开(公告)日：2024-07-04

申请号：US18602594

申请日：2024-03-12

申请人： FUJIAN JINHUA INTEGRATED CIRCUIT CO., LTD.

发明人： Yi-Wang JHAN ,  Yung-Tai HUANG ,  Xin YOU ,  Xiaopei FANG ,  Yu-Cheng TUNG

IPC分类号： H01L23/00 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/417

CPC分类号： H01L24/05 ,  H01L21/823462 ,  H01L21/823475 ,  H01L24/03 ,  H01L29/1033 ,  H01L29/41775 ,  H01L2224/036 ,  H01L2224/0508 ,  H01L2224/05099

摘要： A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a plurality of gate conductive patterns on the substrate; an interlayer dielectric layer covering the gate conductive patterns on the substrate; an interconnect structure comprising a contact plug and a first contact pad, the contact plug extending through the interlayer dielectric layer to the substrate, the first contact pad fully covering a top of the contact plug and extending laterally over part of a top surface of the interlayer dielectric layer; and a second contact pad formed on the top surface of the interlayer dielectric layer and spaced apart from a side edge of the first contact pad, wherein the second contact pad is formed and fully overlays on the interlayer dielectric layer and an isolation plug is spaced apart from the first contact pad.

公开(公告)号：US12027596B2

公开(公告)日：2024-07-02

申请号：US18201308

申请日：2023-05-24

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC分类号： H01L29/417 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

摘要： A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.