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公开(公告)号：US20220102281A1
公开(公告)日：2022-03-31
申请号：US17033655
申请日：2020-09-25
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00 , H01L23/14
摘要： A digitally communicative circuit may use standardized interfaces for connection and communication with other circuit components. Such digitally communicative circuit may benefit from using wider variety of interconnect schemes with the respective interfaces for transmission and reception of data. Some chiplets may communicate using a high data bandwidth interface while other chiplets may communicate using interfaces with lower data bandwidth. Alternate interface is introduced that may facilitate scaled communication with Advanced Interface Bus 2.0 without translation circuitry and with different data bandwidth.
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公开(公告)号：US20220336415A1
公开(公告)日：2022-10-20
申请号：US17856193
申请日：2022-07-01
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00
摘要： Systems and methods are provided for a modular die-to-die interconnect for integrated circuits in a three-dimensional arrangement. An integrated circuit system may include a first chiplet that includes a grid-based interconnect field and a second chiplet that includes a complementary grid-based interconnect field. A number of interconnects of the complementary grid-based interconnect field of the second chiplet are connected to a corresponding number of interconnects of the grid-based interconnect field of the first chiplet.
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公开(公告)号：US20220337251A1
公开(公告)日：2022-10-20
申请号：US17856643
申请日：2022-07-01
IPC分类号： H03K19/17796 , G06F30/347 , H03K19/17736 , H01L25/065
摘要： Systems and methods are provided for system circuitry disaggregation into an integrated circuit system with multiple chiplets having disaggregated components. A system may include a first programmable logic fabric die that includes programmable logic circuitry and a number of supporting chiplets that include disaggregated field programmable gate array (FPGA) circuitry. The chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement.
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公开(公告)号：US20230024662A1
公开(公告)日：2023-01-26
申请号：US17957217
申请日：2022-09-30
IPC分类号： H01L23/528 , H01L23/525 , H01L23/00 , H03K19/17736 , H01L25/065 , H03K19/1776
摘要： A die includes one or more power delivery layers to deliver power within the die. Additionally, the die also includes one or more transistor layers to at least partially implement a programmable fabric for the die. Furthermore, the die further includes one or more signal routing layers to transmit signals for use by the programmable fabric. Moreover, the one or more transistor layers physically separate the one or more power delivery layers from the one or more signal routing layers.
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公开(公告)号：US20230028475A1
公开(公告)日：2023-01-26
申请号：US17957204
申请日：2022-09-30
IPC分类号： H01L23/538 , H01L23/498 , H03K19/17736 , H03K19/1776 , H01L25/065
摘要： A system includes a first die having a first side with first die-to-die circuitry and first input output circuitry. The system also includes a second die comprising a second side with second die-to-die circuitry and second input output circuitry. The first and second sides are adjacent to each other in the electronic package device. The system also includes a semiconductor interconnect including multiple connections to interconnect the first and second die-to-die circuitries. The semiconductor interconnect also includes multiple through-silicon-vias to transmit data to or from the first and second input output circuitries through the semiconductor bridge.
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公开(公告)号：US20220337250A1
公开(公告)日：2022-10-20
申请号：US17856479
申请日：2022-07-01
IPC分类号： H03K19/17736 , H03K19/1776 , H03K19/17728
摘要： This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.
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公开(公告)号：US20220229941A1
公开(公告)日：2022-07-21
申请号：US17711779
申请日：2022-04-01
摘要： Systems or methods of the present disclosure may provide a semiconductor device including a die of a multi-die package including encryption circuitry to receive data and to encrypt the data to generate encrypted data; and a connection interface to transmit the encrypted data over a die-to-die interconnect to a second die.
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公开(公告)号：US20230042718A1
公开(公告)日：2023-02-09
申请号：US17956372
申请日：2022-09-29
IPC分类号： G06F30/373 , G06F30/34
摘要： Systems or methods of the present disclosure may provide an integrated circuit system. The integrated circuit system may implement a circuit design. Design software models a circuit design for the integrated circuit system and the circuit design is agnostic of physical layer circuitry of the integrated circuit system. The design software may generate configuration data based on the circuit design and transfer the configuration data to the integrated circuit system to cause programmable logic of the integrated circuit system to implement the circuit design.
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公开(公告)号：US20220224342A1
公开(公告)日：2022-07-14
申请号：US17711784
申请日：2022-04-01
摘要： A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.
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公开(公告)号：US20190326210A1
公开(公告)日：2019-10-24
申请号：US16456647
申请日：2019-06-28
申请人： Chee Hak Teh , Chee Seng Leong , Lai Guan Tang , Han Wooi Lim , Hee Kong Phoon
发明人： Chee Hak Teh , Chee Seng Leong , Lai Guan Tang , Han Wooi Lim , Hee Kong Phoon
IPC分类号： H01L23/528 , H01L23/498 , H03K19/177
摘要： The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
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