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1.发明授权Method and system for expressing the algorithms for the manipulation of hardware state using an abstract language 有权使用抽象语言表达用于操纵硬件状态的算法的方法和系统公开(公告)号：US07367016B2
公开(公告)日：2008-04-29
申请号：US10618829
申请日：2003-07-14
CPC分类号： G06F8/31
摘要： A method for expressing the algorithms for the manipulation of hardware includes providing program instructions that describe a sequence of one or more transactions for manipulating hardware components of a system. The program instructions may call one or more code segments that include specific information associated with particular hardware components of the system. In addition, the program instructions are independent of the specific information. The method may also include translating the program instructions into an executable form and executing the executable form of the program instructions to manipulate the hardware components of the system from one consistent state to a next consistent state.
摘要翻译： 用于表达用于硬件操纵的算法的方法包括提供描述用于操纵系统的硬件组件的一个或多个事务的序列的程序指令。 程序指令可以调用包括与系统的特定硬件组件相关联的特定信息的一个或多个代码段。 此外，程序指令独立于具体信息。 该方法还可以包括将程序指令转换成可执行形式并且执行程序指令的可执行形式以将系统的硬件组件从一个一致状态操纵到下一个一致状态。
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公开(公告)号：US06425094B1
公开(公告)日：2002-07-23
申请号：US09371059
申请日：1999-08-09
IPC分类号： H02H305
CPC分类号： G06F11/2284 , G06F11/20
摘要： A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.
摘要翻译： 公开了一种多处理器系统，其采用用于笼罩冗余组件以允许对冗余组件进行测试而不干扰正常系统操作的装置和方法。 在一个实施例中，多处理器系统包括由网络互连的至少两个系统控制器和一组处理节点。 系统控制器分配和配置系统资源，并且处理节点各自包括将节点耦合到系统控制器的节点接口。 节点接口可以单独地和分离地配置为笼式和非笼状模式。 在未采集模式下，节点接口将信息从任一系统控制器传送到处理节点中的其他组件。 在笼式模式中，节点接口检查来自至少一个系统控制器的信息。
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3.发明授权Dynamic self-tuning soft-error-rate-discrimination for enhanced availability of enterprise computing systems 有权动态自整定软错误率歧视，增强企业计算系统的可用性公开(公告)号：US07526683B1
公开(公告)日：2009-04-28
申请号：US11141844
申请日：2005-06-01
IPC分类号： G06F11/00
CPC分类号： G06F11/008
摘要： A method for use in a computer system provides a dynamic, “self tuning” soft-error-rate-discrimination (SERD) method and apparatus. Specially designed SRAMs or other circuits are “tuned” in a manner that gives them extreme susceptibility to cosmic neutron events (soft errors), higher than that of the “regular” SRAM components, memory modules or other components in the computer system. One such specially designed SRAM is deployed per server. An interface algorithm continuously sends read/write traffic to the special SRAM to infer the soft error rate (SER), which is directly proportional to cosmic neutron flux. The inferred cosmic neutron flux rate is employed in a Poisson SPRT algorithmic approach that dynamically compensates the soft error discrimination sensitivity in accordance with the instantaneous neutron flux for all of the regular SRAM components in the server.
摘要翻译： 一种在计算机系统中使用的方法提供了一种动态的“自调谐”软错误率鉴别（SERD）方法和装置。 专门设计的SRAM或其他电路以“调谐”的方式使其对宇宙中子事件（软错误）具有极高的敏感性，高于计算机系统中“常规”SRAM组件，存储器模块或其他组件的极端敏感性。 每个服务器部署一个这样专门设计的SRAM。 接口算法连续向专用SRAM发送读/写流量，推断出与宇宙中子通量成正比的软误码率（SER）。 推测的宇宙中子通量速率采用泊松SPRT算法方法，根据服务器中所有常规SRAM组件的瞬时中子通量动态补偿软误差鉴别灵敏度。
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公开(公告)号：US06760868B2
公开(公告)日：2004-07-06
申请号：US10170928
申请日：2002-06-13
IPC分类号： G06F1100
CPC分类号： G06F11/2284 , G06F11/20
摘要： A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers. When all node interfaces censor information from a common system controller, this system controller is effectively “caged” and communications from this system controller are thereby prevented from reaching other node components. This allows the caged system controller along with all its associated interconnections to be tested without interfering with normal operation of the system. Normal system configuration tasks are handled by the uncaged system controller. The uncaged system controller can instruct the node interfaces to uncage the caged system controller if the tests are successfully completed.
摘要翻译： 公开了一种多处理器系统，其采用用于笼罩冗余组件以允许对冗余组件进行测试而不干扰正常系统操作的装置和方法。 在一个实施例中，多处理器系统包括由网络互连的至少两个系统控制器和一组处理节点。 系统控制器分配和配置系统资源，并且处理节点各自包括将节点耦合到系统控制器的节点接口。 节点接口可以单独地和分离地配置为笼式和非笼状模式。 在未采集模式下，节点接口将信息从任一系统控制器传送到处理节点中的其他组件。 在笼式模式中，节点接口检查来自至少一个系统控制器的信息。 当所有节点接口从公共系统控制器审查信息时，该系统控制器被有效地“笼罩”，从而防止来自该系统控制器的通信到达其他节点组件。 这允许笼式系统控制器及其所有相关联的互连进行测试，而不会干扰系统的正常操作。 正常系统配置任务由未分层系统控制器处理。 如果测试成功完成，则未分级系统控制器可以指示节点接口对笼式系统控制器进行解包。
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公开(公告)号：US06571360B1
公开(公告)日：2003-05-27
申请号：US09422204
申请日：1999-10-19
申请人： Daniel P. Drogichen , Eric Eugene Graf , Don Kane , Douglas B. Meyer , Andrew E. Phelps , Patricia Shanahan , Steven F. Weiss
发明人： Daniel P. Drogichen , Eric Eugene Graf , Don Kane , Douglas B. Meyer , Andrew E. Phelps , Patricia Shanahan , Steven F. Weiss
IPC分类号： G06F1100
CPC分类号： G06F11/2733
摘要： A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested. The error cage isolates correction code errors, parity errors, protocol errors, timeout errors, and other similar errors generated by the I/O board under test. The address transaction cage isolates out of range memory addresses from the I/O board under test. The interrupt transaction cage isolates interrupt requests to an incorrect target port generated by the I/O board under test. The errors generated by the I/O board are logged in a status register and suppressed.
摘要翻译： 多处理计算机系统提供硬件支持，以正确测试I / O板，同时系统正在运行用户应用程序，同时防止故障板导致系统崩溃。 该系统包括一个安装多个扩展板的中心平面。 每个扩展板又将微处理器板和I / O板连接到中心面。 在进行测试之前，替换I / O板在插入多处理计算机系统的扩展板之后，将成为动态系统域软件分区的一部分。 测试I / O板涉及在微处理器板上执行一个使用微处理器和存储器的过程来对I / O板进行硬件测试。 错误笼，地址事务笼和中断事务笼隔离在测试I / O板时产生的任何错误。 错误笼隔离了被测I / O板产生的校正码错误，奇偶校验错误，协议错误，超时错误以及其他类似的错误。 地址事务笼隔离来自被测I / O板的范围内的存储器地址。 中断事务笼将中断请求隔离到被测I / O板产生的目标端口不正确。 I / O板产生的错误记录在状态寄存器中并被抑制。
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