公开(公告)号：US20170347150A1

公开(公告)日：2017-11-30

申请号：US15586742

申请日：2017-05-04

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojoo LEE ,  Sukho LEE ,  Kyung Jin BYUN ,  Sung Weon KANG

IPC: H04N21/443 ,  H04N21/234 ,  H04N21/45 ,  H04N21/61

CPC classification number: H04N21/4436 ,  H04N21/23418 ,  H04N21/23614 ,  H04N21/44 ,  H04N21/4516 ,  H04N21/6125

Abstract: Provided is a video providing system. The video providing system includes a memory configured to store device information of a display device, an analyzer configured to receive an original video from the outside and analyze images in the original video, and a processor configured to generate, from the original video, video streams according to a streaming mode and control signals of the display device respectively corresponding to the video streams, based on device information of a display device and analysis information from the analyzer, and provide the video streams and the control signals to the display device.

公开(公告)号：US20180109415A1

公开(公告)日：2018-04-19

申请号：US15644434

申请日：2017-07-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kyuseung HAN ,  Woojoo LEE ,  Jae-Jin LEE ,  Sung Weon KANG

IPC: H04L12/24 ,  H03K17/14 ,  H04L12/933

CPC classification number: H04L41/0803 ,  H01L29/785 ,  H03K17/145 ,  H03K19/0016 ,  H03K19/00384 ,  H04L41/0672 ,  H04L43/08 ,  H04L49/101

Abstract: Provided is a network-on-chip (NoC). The NoC includes a plurality of routers configured to receive power through each corresponding power gating switch, and a controller configured to control a power gating switch of each of the plurality of routers based on temperature information provided from each of the plurality of routers and control a driving clock of the plurality of routers. The controller controls the power gating switch to turn off at least one first router by referring to the temperature information and over-scale a clock frequency of at least one turned-on second router.

公开(公告)号：US20180145671A1

公开(公告)日：2018-05-24

申请号：US15725905

申请日：2017-10-05

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Woojoo LEE ,  Jae-Jin LEE ,  Sukho LEE ,  Kyuseung HAN ,  Sang Pil KIM ,  Young Hwan BAE

IPC: H03K5/134

CPC classification number: H03K5/134 ,  H03K2005/00143

Abstract: Provided is a semiconductor device including a target circuit, a monitoring circuit, and a voltage controller. The target circuit includes a transistor. The monitoring circuit is configured to measure a temperature of the target circuit or measure a delay time between an input and an output of the target circuit. The voltage controller is configured to adjust a driving voltage for driving the target circuit or a back-bias voltage for adjusting a threshold voltage of the transistor by referring to at least one of the temperature and the delay time. As the temperature increases, the delay time decreases.

公开(公告)号：US20170222648A1

公开(公告)日：2017-08-03

申请号：US15414236

申请日：2017-01-24

Applicant: Electronics and Telecommunications Research Institute

Inventor： Woojoo LEE ,  Young-Su KWON ,  Kyung Jin BYUN ,  Jin Ho HAN ,  Nak Woong EUM

IPC: H03K19/00

CPC classification number: H03K19/0013 ,  G06F3/0202 ,  H01L27/1104 ,  H01L29/49 ,  H03K17/9638 ,  H03K19/00369 ,  H03K19/0944

Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.