-
公开(公告)号：US12182538B2
公开(公告)日：2024-12-31
申请号：US18182345
申请日：2023-03-12
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Joseph Rifkin , Ahmed Eshra , Sithara Priyadarshini , Rohan Patel
Abstract: A method includes providing one or more application developers with a selection of a multitude of features to add to the device application, the selection includes a computer readable specification where each of the multitude of features are implemented by one or more building block components, that include one or more functions, which are automatically certified via a certification process upon submission by a building block developer and each of the one or more building block components are configured to be operated by a run engine that facilitates communication between building block components of the device application. The method includes verifying that the selection of the multitude of features are performed by a selection of the one or more building block components and generating the device application. The device application includes the selection of the one or more building block components.
-
公开(公告)号：US20240303046A1
公开(公告)日：2024-09-12
申请号：US18182344
申请日：2023-03-12
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Joseph Rifkin , Ahmed Eshra , Sithara Priyadarshini , Rohan Patel
Abstract: Systems, methods, and computer readable storage mediums for generating a device application are disclosed. A method includes certifying a multitude of building block components, each of the multitude of building block components including functions that operate independently from other building block components. The building block components are configured to deliver one or more features of a device application that operates a run engine that facilitates communication between building blocks of the device application. The method further includes providing the multitude of building block components in a library for one or more developers of the device application and generating a computer-readable specification for the device application, the computer-readable specification includes one or more of the multitude of building block components.
-
公开(公告)号：US20240403000A1
公开(公告)日：2024-12-05
申请号：US18325023
申请日：2023-05-29
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Utsav Preet , Sithara Priyadarshini , Rohan Patel
IPC: G06F8/33
Abstract: Systems and methods for merging one or more codes is disclosed. The system includes a processor coupled to a memory. The processor is configured to receive a request for creating a build card. The request includes one or more designs and one or more functions. The processor is further configured to convert the one or more designs into one or more design codes. The processor is further configured to determine one or more functional codes for implementing the one or more functions. The one or more functional codes are determined by analyzing one or more building blocks corresponding to one or more previously developed projects. In addition, the processor is configured to merge the one or more design codes with at least one functional code corresponding to at least one building block to generate a merged output.
-
公开(公告)号：US20240394046A1
公开(公告)日：2024-11-28
申请号：US18323410
申请日：2023-05-25
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Joseph Rifkin , Sithara Priyadarshini , Rohan Patel
Abstract: Systems and methods for assembling source codes of one or more projects is disclosed. The system includes a processor coupled to a memory. The processor is configured to receive a request for accessing source codes of one or more features assigned for the one or more projects. The source codes are stored in a code repository. The processor is further configured to share development details of the source codes received from the code repository to one or more developers working on the one or more projects. The processor is further configured to determine one or more customizable areas of the source codes and present the one or more customizable areas to the one or more developers. In addition, the processor is configured to receive one or more upgrades made in the one or more customizable areas of the source codes.
-
公开(公告)号：US20240338636A1
公开(公告)日：2024-10-10
申请号：US18295838
申请日：2023-04-04
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Utsav Preet , Sithara Priyadarshini , Rohan Patel
IPC: G06Q10/0639 , G06Q10/0631
CPC classification number: G06Q10/06398 , G06Q10/063112
Abstract: Systems, methods, and computer readable storage mediums for evaluating a developer of a device application are disclosed. A method includes receiving a classification for an application developer and determining, based on the classification, one or more tests to verify the classification. The method further includes assigning a job, based on the classification, to the developer, the job determined by a machine readable specification. The method further includes determining a quality of a completed job and updating the classification of the application developer based on the quality of the completed job.
-
Patent Agency Ranking
公开(公告)号：US20240403195A1
公开(公告)日：2024-12-05
申请号：US18325025
申请日：2023-05-29
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Utsav Preet , Sithara Priyadarshini , Rohan Patel
IPC: G06F11/36
Abstract: Systems and methods for testing one or more code merges is disclosed. The system includes a processor coupled to a memory. The processor is configured to receive a request for merging one or more design codes corresponding to one or more designs of a build card with one or more functional codes for generating a merged output. The processor is further configured to capture one or more output screenshots of the merged output. In addition, the processor is configured to evaluate the merged output by comparing the one or more output screenshots with one or more input screenshots that include the one or more designs prior to the generation of the merged output.
-
公开(公告)号：US20240394047A1
公开(公告)日：2024-11-28
申请号：US18323412
申请日：2023-05-25
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Joseph Rifkin , Sithara Priyadarshini , Rohan Patel
Abstract: Systems and methods for managing one or more building blocks of one or more projects is disclosed. The system includes a processor coupled to a memory. The processor is configured to receive a request for completing one or more projects. The request includes one or more features assigned for each project and one or more building blocks that implement the one or more features. The processor is further configured to assign one or more developers to complete the one or more projects. The one or more developers are assigned based on a selection criteria. The processor is further configured to capture one or more modifications made by the one or more developers to at least one building block. In addition, the processor is configured to generate a project pipeline that presents the one or more modifications captured.
-
公开(公告)号：US20240338180A1
公开(公告)日：2024-10-10
申请号：US18295840
申请日：2023-04-04
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Utsav Preet , Sithara Priyadarshini , Rohan Patel
IPC: G06F8/20
CPC classification number: G06F8/20
Abstract: Systems, methods, and computer readable storage mediums for developing a building component for a device application are disclosed. A method includes testing a first developer on a proficiency to develop building components, each of the building components comprising one or more functions that operate independently of other building components and determining a classification of the developer based on the testing. The method further includes assigning a first job, based on the classification, to the first developer to develop a first building component and evaluating a first completed building component to update the classification, the first completed building component based on the job to develop the first building component.
-
公开(公告)号：US20240403034A1
公开(公告)日：2024-12-05
申请号：US18325024
申请日：2023-05-29
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Utsav Preet , Sithara Priyadarshini , Rohan Patel
Abstract: Systems and methods for managing one or more code merges is disclosed. The system includes a processor coupled to a memory. The processor is configured to receive a request for merging one or more design codes corresponding to one or more designs of a build card with one or more functional codes for generating a merged output. The processor is further configured to generate a merge summary for one or more users that presents the merged output. In addition, the processor is configured to generate a project workflow for completing the build card. The project workflow is generated based on the merged output and one or more parameters.
-
公开(公告)号：US20240394052A1
公开(公告)日：2024-11-28
申请号：US18323411
申请日：2023-05-25
Applicant: Engineer.ai Corp.
Inventor： Sachin Dev Duggal , Joseph Rifkin , Sithara Priyadarshini , Rohan Patel
IPC: G06F8/77
Abstract: Systems and methods for managing changes implemented in one or more projects is disclosed. The system includes a processor coupled to a memory. The processor is configured to receive a request for completing one or more projects. The request includes one or more features assigned for each project and one or more building blocks that implement the one or more features. The processor is further configured to assign one or more developers to complete the one or more projects. The one or more developers are assigned based on a selection criteria. The processor is further configured to capture one or more modifications made by the one or more developers to at least one building block. In addition, the processor is configured to generate a project pipeline that presents the one or more modifications captured.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.017 seconds)
