公开(公告)号：US11177932B1

公开(公告)日：2021-11-16

申请号：US17234832

申请日：2021-04-20

Applicant: Faraday Technology Corp.

Inventor： Vinay Suresh Rao ,  Andrew Chao

IPC: H04L7/033 ,  H03M9/00 ,  H03H17/02

Abstract: A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.