公开(公告)号：US20210313970A1

公开(公告)日：2021-10-07

申请号：US17178194

申请日：2021-02-17

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： LING CHEN ,  Andrew Chao ,  XIAO-DONG FEI

IPC: H03K3/012 ,  H03K5/01 ,  H03K5/1252 ,  H03K3/037 ,  H04B1/16

Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

公开(公告)号：US11177932B1

公开(公告)日：2021-11-16

申请号：US17234832

申请日：2021-04-20

Applicant: Faraday Technology Corp.

Inventor： Vinay Suresh Rao ,  Andrew Chao

IPC: H04L7/033 ,  H03M9/00 ,  H03H17/02

Abstract: A clock generation circuit for generating a plurality of output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals, and a DC signal; a first polyphase filter for generating four clock signals from the differential clock signals which are a quadrature phase apart from each other; a plurality of setting buffers for setting a same DC point for the four clock signals and generating four resultant clock signals; coupled polyphase filters for generating four more clock signals which are a quadrature apart from each other, and outputting the resultant eight clock signals; a phase mixer, for generating eight output clock signals 45 degrees apart from each other; and a plurality of restoration buffers for setting a DC point for each of the eight clock signals and generating eight output clock signals all riding on a same DC point.

公开(公告)号：US11381222B2

公开(公告)日：2022-07-05

申请号：US17178194

申请日：2021-02-17

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Ling Chen ,  Andrew Chao ,  Xiao-Dong Fei

IPC: H03K3/012 ,  H03K5/01 ,  H03K5/1252 ,  H03K5/00 ,  H04B1/16 ,  H03K3/037 ,  H03K19/20

Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

公开(公告)号：US10855437B1

公开(公告)日：2020-12-01

申请号：US16583234

申请日：2019-09-25

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Ling Chen ,  Andrew Chao ,  Xiao-Dong Fei ,  Wei Liu

IPC: H04L7/033 ,  H03L7/08

Abstract: The present invention provides a clock data recovery apparatus and an operation method thereof. The clock data recovery apparatus includes an equalizer, a phase detector, a charge pump, and an oscillation circuit. The equalizer is configured to equalize raw data to generate equalized data. The phase detector is coupled to the equalizer to receive the equalized data. The phase detector is configured to generate a detection result according to the equalized data. The phase detector performs pattern-filtering on the equalized data to filter out at least one pattern. The charge pump is coupled to the phase detector to receive the detection result. The charge pump is configured to generate a control signal according to the detection result. The oscillation circuit is coupled to the charge pump to receive the control signal. The oscillation circuit is configured to generate a clock signal according to the control signal.