公开(公告)号：US11032055B1

公开(公告)日：2021-06-08

申请号：US17006904

申请日：2020-08-31

Applicant: Faraday Technology Corp.

Inventor： Yu-Hsin Tseng

IPC: H03L7/087 ,  H04L7/033 ,  H03K3/037 ,  H03L7/089 ,  G06F1/12

Abstract: A clock data recovery circuit including a phase blender, a phase detector, a data sampling position detector and a data selector is provided. The phase blender generates a third clock signal and a fourth clock signal according to a first clock signal and a second clock signal. The phase detector samples a data signal according to the first and second clock signals to generate first sampled data, second sampled data and a phase state signal. The data sampling position detector samples the data signal according to the third and fourth clock signals to generate third sampled data, fourth sampled data and a control signal. The data selector generates output data according to the control signal and the phase state signal.

公开(公告)号：US11582018B2

公开(公告)日：2023-02-14

申请号：US17394299

申请日：2021-08-04

Applicant: Faraday Technology Corp.

Inventor： Jing-Zhi Gao ,  Yu-Hsin Tseng ,  Yung-Sung Chang ,  Zhi-Xin Lin

IPC: H04L7/00

Abstract: A clock data calibration circuit including a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparators and a data selector is provided. The first comparator compares first input data with second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, and the clock signals are divided into a plurality of clock groups. The sampler samples the data signal according to the clock groups to respectively generate a plurality of first sampled data signal groups. The data comparators respectively sample the first sampled data signal groups according to selected clocks to generate a plurality of second sampled data signal groups. Each data comparator generates a plurality of status flags according to a variation state of a plurality of second sampled data. The data selector generates a plurality of output data signals according to the status flags.

公开(公告)号：US20220337385A1

公开(公告)日：2022-10-20

申请号：US17394299

申请日：2021-08-04

Applicant: Faraday Technology Corp.

Inventor： Jing-Zhi Gao ,  Yu-Hsin Tseng ,  Yung-Sung Chang ,  Zhi-Xin Lin

IPC: H04L7/00

Abstract: A clock data calibration circuit including a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparators and a data selector is provided. The first comparator compares first input data with second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, and the clock signals are divided into a plurality of clock groups. The sampler samples the data signal according to the clock groups to respectively generate a plurality of first sampled data signal groups. The data comparators respectively sample the first sampled data signal groups according to selected clocks to generate a plurality of second sampled data signal groups. Each data comparator generates a plurality of status flags according to a variation state of a plurality of second sampled data. The data selector generates a plurality of output data signals according to the status flags.