公开(公告)号：US20140179093A1

公开(公告)日：2014-06-26

申请号：US13721132

申请日：2012-12-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Dae-Han CHOI ,  Wontae HWANG ,  Puneet KHANNA

IPC: H01L21/283

CPC classification number: H01L29/66583 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: Gate structures and methods of fabricating gate structures of semiconductor devices are provided. One method includes, for instance: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a gate opening within the sacrificial layer; providing a gate structure within the gate opening in the sacrificial layer; and removing the sacrificial layer, leaving the gate structure over the substrate. In enhanced aspects, the method includes: forming a reverse sidewall-spacer within the gate opening within the sacrificial layer, and after providing the gate structure, recessing the gate structure within the gate opening, and providing a gate cap within the gate recess in the gate structure.

Abstract translation: 提供了栅极结构和制造半导体器件的栅极结构的方法。 一种方法包括例如：在衬底上提供牺牲层; 图案化牺牲层以在牺牲层内形成栅极开口; 在所述牺牲层中的所述栅极开口内提供栅极结构; 并去除牺牲层，将栅极结构留在衬底上。 在增强的方面，该方法包括：在牺牲层内的栅极开口内形成反向侧壁间隔物，并且在提供栅极结构之后，在栅极开口内凹入栅极结构，并且在栅极凹部内提供栅极盖 门结构。

公开(公告)号：US20140199845A1

公开(公告)日：2014-07-17

申请号：US13740343

申请日：2013-01-14

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Dae-Han CHOI ,  Dae Geun YANG ,  Chang Ho MAENG ,  Wontae HWANG

IPC: H01L29/40

CPC classification number: H01L29/401 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods are provided for facilitating fabricating a semiconductor device by selectively etching a gate structure sidewall(s) to facilitate subsequent sidewall spacer isolation. The method includes, for instance: providing a gate structure with a protective layer(s) over the gate structure, the gate structure including one or more sidewalls; selectively removing a portion of the gate structure along at least one sidewall to partially undercut the protective layer(s); and forming a sidewall spacer(s) over the sidewall(s) of the gate structure, with a portion of the sidewall spacer at least partially filling the partial undercut of the protective layer(s), and residing below the protective layer(s). In certain embodiments, the selectively removing includes implanting the sidewall(s) with a dopant to produce a doped region(s) of the gate structure, and subsequently, at least partially removing the doped region(s) of the gate structure selective to an undoped region of the gate structure.

Abstract translation: 提供了通过选择性地蚀刻栅极结构侧壁以促进随后的侧壁间隔隔离来促进制造半导体器件的方法。 该方法包括例如：在栅极结构上提供具有保护层的栅极结构，栅极结构包括一个或多个侧壁; 沿着至少一个侧壁选择性地去除所述栅极结构的一部分以部分地切割所述保护层; 以及在所述栅极结构的侧壁上形成侧壁间隔物，所述侧壁间隔物的一部分至少部分地填充所述保护层的部分底切，并且位于所述保护层下方， 。 在某些实施例中，选择性去除包括用掺杂剂注入侧壁以产生栅极结构的掺杂区域，并且随后至少部分地去除栅极结构的掺杂区域， 栅极结构的未掺杂区域。