公开(公告)号：US20240363723A1

公开(公告)日：2024-10-31

申请号：US18140850

申请日：2023-04-28

申请人： Applied Materials, Inc.

发明人： Srinivas Gandikota ,  Tengzhou Ma ,  Geetika Bajaj ,  Debaditya Chatterjee ,  Hsin-Jung Yu ,  Pei Hsuan Lin ,  Yixiong Yang

IPC分类号： H01L29/51 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40

CPC分类号： H01L29/513 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/401 ,  H01L29/517

摘要： Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.

公开(公告)号：US20240363338A1

公开(公告)日：2024-10-31

申请号：US18766582

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chi-Chang Liu

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L29/51

CPC分类号： H01L21/02211 ,  H01L21/02126 ,  H01L23/53295 ,  H01L29/517

摘要： A method of forming a semiconductor device includes the following operations. A substrate is provided with a device and an insulating layer disposed over the device. A silicon-containing heterocyclic compound precursor and a first oxygen-containing compound precursor are introduced to the substrate, so as to form a zeroth dielectric layer on the insulating layer. A zeroth metal layer is formed in the zeroth dielectric layer. A silicon-containing linear compound precursor and a second oxygen-containing compound precursor are introduced to the substrate to form a first dielectric layer on the zeroth dielectric layer. A first metal layer is formed in the first dielectric layer.

公开(公告)号：US20240332359A1

公开(公告)日：2024-10-03

申请号：US18739519

申请日：2024-06-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Yu CHEN ,  Chung-Liang CHENG

IPC分类号： H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.

公开(公告)号：US12108604B2

公开(公告)日：2024-10-01

申请号：US17479789

申请日：2021-09-20

申请人： Applied Materials, Inc.

发明人： Jaesoo Ahn ,  Thomas Kwon ,  Mahendra Pakala

IPC分类号： H10B51/20 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B51/20 ,  H01L21/02164 ,  H01L21/02236 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/31116

摘要： Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US20240322037A1

公开(公告)日：2024-09-26

申请号：US18651184

申请日：2024-04-30

申请人： Sony Group Corporation

发明人： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R.C. Post

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645 ,  H01L29/42376

摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

公开(公告)号：US12100753B2

公开(公告)日：2024-09-24

申请号：US18361758

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

发明人： Jenn-Gwo Hwu ,  Chien-Shun Liao

IPC分类号： H01L29/739 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7391 ,  H01L21/28088 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/423 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66356 ,  H01L21/26513

摘要： Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

公开(公告)号：US20240313067A1

公开(公告)日：2024-09-19

申请号：US18669199

申请日：2024-05-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yen-Tien Tung ,  Szu-Wei Huang ,  Zhi-Ren Xiao ,  Yin-Chuan Chuang ,  Yung-Chien Huang ,  Kuan-Ting Liu ,  Tzer-Min Shen ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC分类号： H01L29/40 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC分类号： H01L29/401 ,  H01L21/32053 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

摘要： A semiconductor structure includes a substrate and a semiconductor channel layer over the substrate. The semiconductor structure includes a high-k gate dielectric layer over the semiconductor channel layer, a work function metal layer over the high-k gate dielectric layer, and a bulk metal layer over the work function metal layer. The work function metal layer includes a first portion and a second portion over the first portion. Both the first portion and the second portion are conductive. Materials included in the second portion are also included in the first portion. The first portion is doped with silicon at a first dopant concentration, and the second portion is not doped with silicon or is doped with silicon at a second dopant concentration lower than the first dopant concentration.

公开(公告)号：US20240313040A1

公开(公告)日：2024-09-19

申请号：US18673308

申请日：2024-05-24

申请人： SK hynix Inc.

发明人： Se Hun KANG

IPC分类号： H01L29/51 ,  H10B53/30 ,  H10B51/20

CPC分类号： H01L28/56 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H10B53/30 ,  H10B51/20

摘要： A semiconductor device includes a first electrode, a second electrode, and a multi-layer stack positioned between the first electrode and the second electrode, the multi-layer stack including at least one anti-ferroelectric layer and at least one high-k dielectric layer.

公开(公告)号：US20240312991A1

公开(公告)日：2024-09-19

申请号：US18121720

申请日：2023-03-15

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Shao Ming KOH ,  David J. TOWNER

IPC分类号： H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/775

CPC分类号： H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/775

摘要： Gate-all-around integrated circuit structures having tuned upper nanowires are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a first dipole material. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric including a second dipole material, wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material.

公开(公告)号：US12094936B2

公开(公告)日：2024-09-17

申请号：US18376014

申请日：2023-10-03

申请人： ASM IP Holding B.V.

发明人： Fu Tang ,  Peng-Fu Hsu ,  Michael Eugene Givens ,  Qi Xie

IPC分类号： H01L29/40 ,  C23C16/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/161 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/408 ,  C23C16/401 ,  C23C16/403 ,  H01L21/02145 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/28158 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/78

摘要： Methods for forming a metal silicate film on a substrate in a reaction chamber by a cyclical deposition process are provided. The methods may include: regulating the temperature of a hydrogen peroxide precursor below a temperature of 70° C. prior to introduction into the reaction chamber, and depositing the metal silicate film on the substrate by performing at least one unit deposition cycle of a cyclical deposition process. Semiconductor device structures including a metal silicate film formed by the methods of the disclosure are also provided.