公开(公告)号：US20160126132A1

公开(公告)日：2016-05-05

申请号：US14527424

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Carsten Grass ,  Martin Trentzsch ,  Sören Jansen

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括在第一器件区域和第二器件区域之间的隔离区域的半导体衬底。 隔离区域包括与第一器件区域相邻的第一部分和与第二器件区域相邻的第二部分。 该方法包括将隔离区域的第二部分选择性蚀刻到第二高度。 该方法在第一器件区域和第二器件区域上形成绝缘层。 所述方法还包括在所述隔离区域的所述第一器件区域和所述第一部分上选择性蚀刻所述绝缘层。 隔离区域的第一部分被蚀刻到基本上等于第二高度的第一高度。

公开(公告)号：US09508588B2

公开(公告)日：2016-11-29

申请号：US14527424

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Carsten Grass ,  Martin Trentzsch ,  Sören Jansen

IPC: H01L21/762 ,  H01L21/266 ,  H01L21/311

CPC classification number: H01L21/76237 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括在第一器件区域和第二器件区域之间的隔离区域的半导体衬底。 隔离区域包括与第一器件区域相邻的第一部分和与第二器件区域相邻的第二部分。 该方法包括将隔离区域的第二部分选择性蚀刻到第二高度。 该方法在第一器件区域和第二器件区域上形成绝缘层。 所述方法还包括在所述隔离区域的所述第一器件区域和所述第一部分上选择性蚀刻所述绝缘层。 隔离区域的第一部分被蚀刻到基本上等于第二高度的第一高度。