公开(公告)号：US10672439B2

公开(公告)日：2020-06-02

申请号：US16031350

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dhani Reddy Sreenivasula Reddy ,  Md Nadeem Iqbal

IPC: G11C7/12 ,  G11C7/06 ,  G11C11/4097 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/18

Abstract: The present disclosure relates to a structure which includes at least one keeper circuit which is configured to hold data to a precharged state during a first operation and be disabled during a second operation.

公开(公告)号：US10381054B1

公开(公告)日：2019-08-13

申请号：US15906588

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dhani Reddy Sreenivasula Reddy ,  Vinay Bhat Soori

IPC: G11C7/00 ,  G11C7/12 ,  G11C5/14 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/419

Abstract: The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.

公开(公告)号：US10199095B1

公开(公告)日：2019-02-05

申请号：US15693637

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dhani Reddy Sreenivasula Reddy ,  Venkatraghavan Bringivijayaraghavan ,  Vinay Bhat Soori

IPC: G11C11/22 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

Abstract: A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.