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公开(公告)号：US10381069B1
公开(公告)日：2019-08-13
申请号：US15891619
申请日：2018-02-08
Applicant: GLOBALFOUNDRIES INC.
Inventor： Sreenivasula Reddy Dhani Reddy , Sreejith Chidambaran , Binu Jose , Venkatraghavan Bringivijayaraghavan
IPC: G11C11/419 , G11C11/412 , G11C7/12 , G11C11/408 , H03K19/177
Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
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公开(公告)号：US09787292B2
公开(公告)日：2017-10-10
申请号：US15003598
申请日：2016-01-21
Applicant: GLOBALFOUNDRIES INC.
Inventor： Venkatraghavan Bringivijayaraghavan
CPC classification number: H03K3/037 , H03K17/005
Abstract: The present disclosure relates to latch structures and, more particularly, to high performance multiplexed latches and methods of use. The multiplexed latch includes: a first latch structured to receive a data signal D0 and comprising a plurality of inverters which receive a respective input clock signal; and a second latch signal structured to receive a data signal D1 and comprising a plurality of inverters which receive a respective input clock signal.
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公开(公告)号：US09721628B1
公开(公告)日：2017-08-01
申请号：US15266261
申请日：2016-09-15
Applicant: GLOBALFOUNDRIES INC.
CPC classification number: G11C7/22 , G11C7/08 , G11C7/1012 , G11C8/08 , G11C8/10 , G11C11/408 , G11C11/418 , G11C11/419 , G11C2207/005
Abstract: Data paths are provided to a memory array. The data paths include switches for selectively aligning the data paths to different multiplexors for reading or writing to the memory array. Read data lines are steered to selected sense amplifiers based on the decode address, using the switches. Write data lines are steered to selected write drivers based on the decode address, using the switches.
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公开(公告)号：US20170214394A1
公开(公告)日：2017-07-27
申请号：US15003598
申请日：2016-01-21
Applicant: GLOBALFOUNDRIES INC.
Inventor： Venkatraghavan Bringivijayaraghavan
CPC classification number: H03K3/037 , H03K17/005
Abstract: The present disclosure relates to latch structures and, more particularly, to high performance multiplexed latches and methods of use. The multiplexed latch includes: a first latch structured to receive a data signal D0 and comprising a plurality of inverters which receive a respective input clock signal; and a second latch signal structured to receive a data signal D1 and comprising a plurality of inverters which receive a respective input clock signal.
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公开(公告)号：US20170053694A1
公开(公告)日：2017-02-23
申请号：US14832127
申请日：2015-08-21
Applicant: GLOBALFOUNDRIES Inc.
IPC: G11C11/419
CPC classification number: G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C11/412 , G11C11/413
Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.
Abstract translation: 提供了一种为静态随机存取存储器（SRAM）阵列提供写入辅助的方法。 电路包括连接到SRAM阵列中的单元的控制电路。 所述控制电路被配置为：在对所述单元的写入操作期间，将第一电压施加到所述单元的第一下拉晶体管; 并且在写入操作期间将不同于第一电压的第二电压施加到单元的第二下拉晶体管。
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Patent Agency Ranking
公开(公告)号：US10600474B2
公开(公告)日：2020-03-24
申请号：US16424605
申请日：2019-05-29
Applicant: GLOBALFOUNDRIES INC.
Inventor： Sreenivasula Reddy Dhani Reddy , Sreejith Chidambaran , Binu Jose , Venkatraghavan Bringivijayaraghavan
IPC: G11C11/419 , G11C11/412 , G11C11/408 , G11C7/12 , H03K19/1776
Abstract: A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.
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公开(公告)号：US10510384B2
公开(公告)日：2019-12-17
申请号：US15814969
申请日：2017-11-16
Applicant: GLOBALFOUNDRIES INC.
IPC: G11C11/419 , G11C7/12 , G11C11/4074 , H04L5/22 , G11C11/406 , G11C11/56
Abstract: The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.
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公开(公告)号：US20180083629A1
公开(公告)日：2018-03-22
申请号：US15269139
申请日：2016-09-19
Applicant: GLOBALFOUNDRIES INC.
Inventor： Venkatraghavan Bringivijayaraghavan
IPC: H03K19/0185 , H03K3/356 , G11C11/418
CPC classification number: H03K19/018507 , G11C7/1057 , G11C7/1072 , G11C7/1084 , G11C11/417 , G11C11/418 , H03K3/356 , H03K3/356121 , H03K3/356173 , H03K3/356191
Abstract: The present disclosure relates to integrated level translator and latch circuits and, more particularly, to an integrated level translator and latch circuits for fence architectures in SRAM cells. The integrated level translator and latch for input signals includes a first clock (CLKS) and a second clock (CLKH). The first clock (CLKS) is used as a precharge and evaluation clock with its timing being critical for forward edge and the second clock (CLKH) is a latch clock.
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公开(公告)号：US20170249976A1
公开(公告)日：2017-08-31
申请号：US15054553
申请日：2016-02-26
Applicant: GLOBALFOUNDRIES INC.
Inventor： Venkatraghavan Bringivijayaraghavan , Ramesh Raghavan
IPC: G11C7/06 , G11C11/419 , G11C11/4091 , G11C7/10
CPC classification number: G11C7/065 , G11C7/08 , G11C7/1051 , G11C11/4091 , G11C11/419
Abstract: Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.
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公开(公告)号：US09400602B2
公开(公告)日：2016-07-26
申请号：US14464090
申请日：2014-08-20
Applicant: GLOBALFOUNDRIES INC.
Inventor： Venkatraghavan Bringivijayaraghavan , Saurabh Chadha , Abhijit Saurabh , Saravanan Sethuraman , Kenneth L. Wright
IPC: G06F3/00 , G06F3/06 , G11C5/14 , G11C5/06 , G06F11/16 , G06F11/07 , G06F11/30 , G06F13/40 , G06F13/16 , G06F13/28 , G06F11/20
CPC classification number: G06F3/06 , G06F3/0617 , G06F3/0619 , G06F3/065 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/0727 , G06F11/1666 , G06F11/20 , G06F11/2017 , G06F11/2092 , G06F11/3027 , G06F11/3034 , G06F13/1684 , G06F13/287 , G06F13/4068 , G11C5/06 , G11C5/148 , Y02D10/14 , Y02D10/151
Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.
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