公开(公告)号：US20170193150A1

公开(公告)日：2017-07-06

申请号：US14985686

申请日：2015-12-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amr Y. Abdo ,  Ioana Graur

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.

公开(公告)号：US09904757B2

公开(公告)日：2018-02-27

申请号：US14985686

申请日：2015-12-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amr Y. Abdo ,  Ioana Graur

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068

Abstract: A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.