ISOLATION STRUCTURES OF FINFET SEMICONDUCTOR DEVICES

    公开(公告)号:US20200227323A1

    公开(公告)日:2020-07-16

    申请号:US16246536

    申请日:2019-01-13

    Abstract: A method of fabricating a semiconductor device is provided, which includes providing sacrificial gate structures over a plurality of fins, wherein the sacrificial gate structures include a first sacrificial gate structure and a second sacrificial gate structure. A fin cut process is performed to form a fin cut opening in the first sacrificial gate structure. A gate cut process is performed to form a gate cut opening in the second sacrificial gate structure. A first dielectric layer is deposited in the fin cut opening and the gate cut opening, and the first dielectric layer is recessed in the openings. A second dielectric layer is deposited over the first dielectric layer in the fin cut opening and the gate cut opening to concurrently form a diffusion break structure and a gate cut structure respectively.

    SEMICONDUCTOR STRUCTURE WITH SHAPED TRENCH AND METHODS OF FORMING THE SAME

    公开(公告)号:US20200211903A1

    公开(公告)日:2020-07-02

    申请号:US16237757

    申请日:2019-01-02

    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.

Patent Agency Ranking