公开(公告)号：US20200066586A1

公开(公告)日：2020-02-27

申请号：US16111193

申请日：2018-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： SEAN X LIN ,  RUILONG XIE ,  GUOXIANG NING ,  LEI SUN

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/58 ,  H01L23/522

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

公开(公告)号：US20200098688A1

公开(公告)日：2020-03-26

申请号：US16140545

申请日：2018-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： YONGJUN SHI ,  RUILONG XIE ,  NAN FU ,  CHUN YU WONG

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer with a plurality of first conductive lines formed of a first conductive material in a dielectric layer. At least one via opening is formed over the plurality of first conductive lines and an interconnect via formed of a second conductive material is formed in the via opening, wherein the formed interconnect via has a convex top surface.

公开(公告)号：US20140134836A1

公开(公告)日：2014-05-15

申请号：US13672864

申请日：2012-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： BALASUBRAMANIAN PRANATHARTHIHARAN ,  CHARAN VEERA VENKATA SATYA SURISETTY ,  JUNLI WANG ,  CHANG SEO PARK ,  RUILONG XIE

IPC: H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: Embodiments of the present invention provide a method of forming borderless contact for transistors. The method includes forming a sacrificial gate structure embedded in a first dielectric layer, the sacrificial gate structure including a sacrificial gate and a second dielectric layer surrounding a top and sidewalls of the sacrificial gate; removing a portion of the second dielectric layer that is above a top level of the sacrificial gate to create a first opening surrounded directly by the first dielectric layer; removing the sacrificial gate exposed by the removing of the portion of the second dielectric layer to create a second opening surrounded by a remaining portion of the second dielectric layer; filling the second opening with one or more conductive materials to form a gate of a transistor; and filling the first opening with a layer of dielectric material to form a dielectric cap of the gate of the transistor.

Abstract translation: 本发明的实施例提供了一种形成晶体管的无边界接触的方法。 该方法包括形成嵌入在第一介电层中的牺牲栅极结构，所述牺牲栅极结构包括牺牲栅极和围绕所述牺牲栅极的顶部和侧壁的第二介电层; 去除位于所述牺牲栅极顶层之上的所述第二电介质层的一部分以产生由所述第一介电层直接包围的第一开口; 去除通过去除第二介电层的部分而暴露的牺牲栅极，以产生由第二介电层的剩余部分包围的第二开口; 用一种或多种导电材料填充第二开口以形成晶体管的栅极; 以及用一层介电材料填充第一开口以形成晶体管的栅极的电介质盖。

公开(公告)号：US20180240883A1

公开(公告)日：2018-08-23

申请号：US15955989

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： DANIEL CHANEMOUGAME ,  ANDRE LABONTE ,  RUILONG XIE ,  LARS LIEBMANN ,  NIGEL CAVE ,  GUILLAUME BOUCHE

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/66719 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/13067

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US20180204927A1

公开(公告)日：2018-07-19

申请号：US15408540

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： DANIEL CHANEMOUGAME ,  ANDRE LABONTE ,  RUILONG XIE ,  LARS LIEBMANN ,  NIGEL CAVE ,  GUILLAUME BOUCHE

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/66719 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/13067

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US20180182668A1

公开(公告)日：2018-06-28

申请号：US15851774

申请日：2017-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： RUILONG XIE ,  CHANRO PARK ,  ANDRE LABONTE ,  LARS LIEBMANN

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/535 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

公开(公告)号：US20170012105A1

公开(公告)日：2017-01-12

申请号：US15273777

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： QING LIU ,  RUILONG XIE ,  CHUN-CHEN YEH

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

Abstract translation: 从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。 用于金属栅电极的功函数金属设置在第一和第二开口中。 沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。 钨层的厚度基本上等于第一开口的长度。 第三个开口填充绝缘材料。 然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。 然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。

公开(公告)号：US20200227323A1

公开(公告)日：2020-07-16

申请号：US16246536

申请日：2019-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： HUI ZANG ,  RUILONG XIE ,  JESSICA MARY DECHENE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

Abstract: A method of fabricating a semiconductor device is provided, which includes providing sacrificial gate structures over a plurality of fins, wherein the sacrificial gate structures include a first sacrificial gate structure and a second sacrificial gate structure. A fin cut process is performed to form a fin cut opening in the first sacrificial gate structure. A gate cut process is performed to form a gate cut opening in the second sacrificial gate structure. A first dielectric layer is deposited in the fin cut opening and the gate cut opening, and the first dielectric layer is recessed in the openings. A second dielectric layer is deposited over the first dielectric layer in the fin cut opening and the gate cut opening to concurrently form a diffusion break structure and a gate cut structure respectively.

公开(公告)号：US20200119002A1

公开(公告)日：2020-04-16

申请号：US16162373

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： RUILONG XIE ,  WILLIAM TAYLOR ,  HUI ZANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure relates to integrated circuit (IC) structures and their method of manufacture. More particularly, the present disclosure relates to forming a semiconductor device having generally fork-shaped contacts around epitaxial regions to increase surface contact area and improve device performance. The integrated circuit (IC) structure of the present disclosure comprises a plurality of fins disposed on a semiconductor substrate, at least one epitaxial region laterally disposed on selected fins, and a contact material positioned over and surrounding the epitaxial region.

公开(公告)号：US20170104082A1

公开(公告)日：2017-04-13

申请号：US14879968

申请日：2015-10-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： XIUYU CAI ,  CHUN-CHEN YEH ,  QING LIU ,  RUILONG XIE

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/51 ,  H01L21/768 ,  H01L29/78 ,  H01L21/311 ,  H01L21/283

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.