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    SEMICONDUCTOR STRUCTURES WITH A PROTECTIVE LINER AND METHODS OF FORMING THE SAME
    1.
    发明申请
    SEMICONDUCTOR STRUCTURES WITH A PROTECTIVE LINER AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20200303247A1

    公开(公告)日：2020-09-24

    申请号：US16355853

    申请日：2019-03-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： JIEHUI SHU ,  HUI ZANG ,  SCOTT HOWARD BEASOR ,  DALI SHAO

    IPC: H01L21/768 ,  H01L29/417

    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a protective liner in transistor devices for protecting one or more gate spacers having a low-K dielectric material. The present disclosure further provides a semiconductor structure including a gate structure having a gate spacer, a trench having upper and lower sidewall portions adjacent to the gate spacer, the trench having a conductive structure over a device element and an adjoining insulative structure over an electrical isolation region, a dielectric liner disposed on the lower sidewall portion of the trench, and a protective liner disposed on the upper sidewall portion of the trench and within the insulative structure.

    MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE
    3.
    发明申请
    MASK-FREE METHODS OF FORMING STRUCTURES IN A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200343142A1

    公开(公告)日：2020-10-29

    申请号：US16396775

    申请日：2019-04-29

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： JIEHUI SHU ,  RINUS TEK PO LEE ,  WEI HONG ,  HUI ZANG ,  HONG YU

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/3065 ,  H01L21/285

    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to replacement metal gate processes and structures for transistor devices having a short channel and a long channel component. The present disclosure also relates to processes and structures for multi-gates with dissimilar threshold voltages. The present disclosure further provides a method of forming structures in a semiconductor device by forming a first and second cavities having sidewalls and bottom surfaces in a dielectric structure, where the first cavity has a narrower opening than the second cavity, forming a first material layer in the first and second cavities, forming a protective layer over the first material layer, where the protective layer fills the first cavity and conformally covers the sidewall and the bottom surfaces of the second cavity, performing a first isotropic etch on the protective layer to selectively remove a portion of the protective layer and form a retained portion of the protective layer, performing a second isotropic etch on the first material layer to selectively remove a portion of the first material layer and form a retained portion of the first material layer, removing the retained portion of the protective layer, and forming a second material layer in the first and second cavities, the second material layer being formed on the retained portion of the first material layer.

    METHOD OF FORMING A VERTICAL FIELD EFFECT TRANSISTOR (VFET) AND A VFET STRUCTURE
    4.
    发明申请
    METHOD OF FORMING A VERTICAL FIELD EFFECT TRANSISTOR (VFET) AND A VFET STRUCTURE 审中-公开

    公开(公告)号：US20180358452A1

    公开(公告)日：2018-12-13

    申请号：US15615925

    申请日：2017-06-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： YI QI ,  JIANWEI PENG ,  HSIEN-CHING LO ,  RUILONG XIE ,  XUNYUAN ZHANG ,  HUI ZANG

    IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

    CPC classification number: H01L29/66666 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66787 ,  H01L29/7827

    Abstract: Disclosed are embodiments of an improved method for forming a vertical field effect transistor (VFET). In each of the embodiments of the method, a semiconductor fin is formed sufficiently thick (i.e., wide) so that the surface area of the top of the semiconductor fin is sufficiently large to facilitate epitaxial growth thereon of a semiconductor material for a second source/drain region. As a result, the second source/drain region will be sufficiently large to avoid potential contact-related defects (e.g., unlanded contacts, complete silicidation of second source/drain region during contact formation, etc.). Additionally, either before or after this second source/drain region is formed, at least the center portion of the semiconductor fin, which will include the channel region of the VFET, is thinned down to a desired critical dimension for optimal VFET performance. Also disclosed are VFET structure embodiments resulting from this method.

    SINGLE-DIFFUSION BREAK STRUCTURE FOR FIN-TYPE FIELD EFFECT TRANSISTORS
    5.
    发明申请
    SINGLE-DIFFUSION BREAK STRUCTURE FOR FIN-TYPE FIELD EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20180374851A1

    公开(公告)日：2018-12-27

    申请号：US15632702

    申请日：2017-06-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： YANZHEN WANG ,  HUI ZANG ,  BINGWU LIU

    IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/535

    Abstract: A method and structure for a semiconductor device that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions, which are within a semiconductor fin and define the active device region(s) for the FINFET(s). Asymmetric trenches are formed in a substrate through asymmetric cuts in sacrificial fins formed on the substrate. The asymmetric cuts have relatively larger gaps between fin portions that are closest to the substrate, and deeper portions of the asymmetric trenches are relatively wider than shallower portions. Channel regions are formed in the substrate below two adjacent fins. Source/drain regions of complementary transistors are formed in the substrate on opposite sides of the channel regions. The asymmetric trenches are filled with an insulator to form a single-diffusion break between two source/drain regions of different ones of the complementary transistors. Also disclosed is a semiconductor structure formed according to the method.

    ISOLATION STRUCTURES OF FINFET SEMICONDUCTOR DEVICES
    8.
    发明申请
    ISOLATION STRUCTURES OF FINFET SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200227323A1

    公开(公告)日：2020-07-16

    申请号：US16246536

    申请日：2019-01-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： HUI ZANG ,  RUILONG XIE ,  JESSICA MARY DECHENE

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762

    Abstract: A method of fabricating a semiconductor device is provided, which includes providing sacrificial gate structures over a plurality of fins, wherein the sacrificial gate structures include a first sacrificial gate structure and a second sacrificial gate structure. A fin cut process is performed to form a fin cut opening in the first sacrificial gate structure. A gate cut process is performed to form a gate cut opening in the second sacrificial gate structure. A first dielectric layer is deposited in the fin cut opening and the gate cut opening, and the first dielectric layer is recessed in the openings. A second dielectric layer is deposited over the first dielectric layer in the fin cut opening and the gate cut opening to concurrently form a diffusion break structure and a gate cut structure respectively.

    SEMICONDUCTOR STRUCTURE WITH SHAPED TRENCH AND METHODS OF FORMING THE SAME
    9.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH SHAPED TRENCH AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20200211903A1

    公开(公告)日：2020-07-02

    申请号：US16237757

    申请日：2019-01-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： JIEHUI SHU ,  JESSICA MARY DECHENE ,  HUI ZANG ,  NAVED AHMED SIDDIQUI

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308

    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.

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