公开(公告)号：US09333735B2

公开(公告)日：2016-05-10

申请号：US14244112

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Patrick A. Raymond

IPC: B32B38/10 ,  B32B43/00 ,  H01L23/00

CPC classification number: B32B43/006 ,  B32B38/10 ,  B32B2307/20 ,  B32B2457/14 ,  H01L21/6835 ,  H01L24/98 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68381 ,  Y10T156/1111

Abstract: Methods for releasing a device substrate temporarily bonded by a bonding layer to a carrier substrate. A dissolution head is engaged with the carrier substrate and a first dissolution process is performed to partially remove the bonding layer. After the first dissolution process is completed, the dissolution head is disengaged from the carrier substrate, and then re-engaged with the carrier substrate. In response to re-engaging the dissolution head with the carrier substrate, a second dissolution process is performed to further remove the bonding layer remaining after the first dissolution process.

Abstract translation: 用于将由接合层暂时接合的器件衬底释放到载体衬底的方法。 溶解头与载体基底接合，并且执行第一溶解过程以部分地去除结合层。 在第一溶出过程完成之后，溶解头与载体基底分离，然后与载体基底重新接合。 响应于将溶解头与载体衬底重新接合，进行第二溶解过程以进一步除去在第一溶解过程之后残留的结合层。

公开(公告)号：US10192748B2

公开(公告)日：2019-01-29

申请号：US15297848

申请日：2016-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy C. Krywanczyk ,  Patrick A. Raymond ,  John C. Hall ,  Damyon L. Corbin

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/265 ,  H01L21/66 ,  H01L21/3215 ,  H01L21/3213

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.

公开(公告)号：US20180108535A1

公开(公告)日：2018-04-19

申请号：US15297848

申请日：2016-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy C. Krywanczyk ,  Patrick A. Raymond ,  John C. Hall ,  Damyon L. Corbin

IPC: H01L21/306 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/30604 ,  H01L21/26533 ,  H01L21/32137 ,  H01L21/3215 ,  H01L21/32155 ,  H01L22/26

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.