CONTROLLING BACK-END-OF-LINE DIMENSIONS OF SEMICONDUCTOR DEVICES

    公开(公告)号:US20200066586A1

    公开(公告)日:2020-02-27

    申请号:US16111193

    申请日:2018-08-23

    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.

Patent Agency Ranking