公开(公告)号：US10447510B1

公开(公告)日：2019-10-15

申请号：US16266707

申请日：2019-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Krishnan S. Rengarajan ,  Vaibhav A. Ruparelia ,  Panduga Shiva Shankar Reddy

IPC: H03H7/30 ,  H04L25/03 ,  H04L27/38

Abstract: Disclosed is a power-optimized distributed arithmetic (DA)-based feed forward equalizer (FFE) that performs on-demand equalization processing of a data sample. Specifically, a data stream is represented by digital words, which indicate signal levels at taps on a transmission medium. A screener applies formulas to selected taps as opposed to all taps (e.g., to the main cursor tap, which corresponds to the current data sample, and to specific pre-cursor and post-cursor taps, which correspond to immediately proceeding and following data samples) to determine whether the current data sample (which should indicate a specific two-bit symbol) has degraded during transmission to a point where equalization processing is required. If so, a bypass flag is set to a first level so that the data sample is subjected to equalization processing. If not, the bypass flag is set to a second level so that such processing is bypassed. Also disclosed is a corresponding method.

公开(公告)号：US10432436B1

公开(公告)日：2019-10-01

申请号：US16216248

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Krishnan S. Rengarajan ,  Vaibhav A. Ruparelia

IPC: G06F1/3203 ,  H04L25/03 ,  H03M7/42 ,  H03K19/177 ,  H04L27/01

Abstract: A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.