-
1.发明授权公开(公告)号：US10432436B1
公开(公告)日：2019-10-01
申请号：US16216248
申请日：2018-12-11
Applicant: GLOBALFOUNDRIES INC.
Inventor： Krishnan S. Rengarajan , Vaibhav A. Ruparelia
IPC: G06F1/3203 , H04L25/03 , H03M7/42 , H03K19/177 , H04L27/01
Abstract: A distributed arithmetic feed forward equalizer (DAFFE) and method. The DAFFE includes look-up tables (LUTs) in offset binary format. A DA LUT stores sum of partial products values and an adjustment LUT stores adjustment values. DA LUT addresses are formed from same-position bits from all but the most significant bits (MSBs) of a set of digital words of taps and an adjustment LUT address is formed using the MSBs. Sum of partial products values and an adjustment value are acquired from the DA LUT and the adjustment LUT using the DA LUT addresses and the adjustment LUT address, respectively. Reduced complexity downstream adder(s) (which result in reduced power consumption) compute a total sum of the sum of partial products values and the adjustment value (which compensates for using the offset binary format and dropping of the MSBs when forming the DA LUT addresses) to correctly solve a DA equation.
-
2.发明授权公开(公告)号：US09324430B2
公开(公告)日：2016-04-26
申请号：US14265409
申请日：2014-04-30
Applicant: GLOBALFOUNDRIES INC.
CPC classification number: G11C16/0466 , G11C11/5692 , G11C16/04 , G11C16/10 , G11C16/28 , G11C17/12 , G11C17/14 , G11C17/18
Abstract: A method of generating a default state in an embedded Multi-Time-Programmable-Read-Only-Memory for a high-performance logic technology consisting of a plurality of memory cells featuring a charge trap, each having a first and a second NMOS transistor. The first and second NMOS transistors use a different mask having different threshold voltages. The second NMOS threshold voltage is adjusted to a middle point of the threshold voltage of the first NMOS with or without trapping the charge. When the charge is not trapped by the first NMOS, the NMOS threshold is lowered to the second NMOS, thereby generating a default state. When the charge is trapped to the first NMOS, the NMOS threshold is higher than the second NMOS, generating a second state. Moreover, a reference voltage generation can use two arrays, each consisting of memory cells and reference memory cells such that a default state can be generated for a single transistor per memory cell.
Abstract translation: 一种用于由具有电荷陷阱的多个存储单元组成的高性能逻辑技术的嵌入式多时间可编程只读存储器中产生默认状态的方法，每个具有第一和第二NMOS晶体管。 第一和第二NMOS晶体管使用具有不同阈值电压的不同掩模。 第二NMOS阈值电压被调整到第一NMOS的阈值电压的中点，不管是否捕获电荷。 当电荷未被第一NMOS捕获时，NMOS阈值降低到第二NMOS，从而产生默认状态。 当电荷被俘获到第一NMOS时，NMOS阈值高于第二NMOS，产生第二状态。 此外，参考电压产生可以使用两个阵列，每个阵列由存储器单元和参考存储器单元组成，使得可以为每个存储器单元的单个晶体管产生默认状态。
-
公开(公告)号：US09251890B1
公开(公告)日：2016-02-02
申请号：US14577113
申请日：2014-12-19
Applicant: GLOBALFOUNDRIES INC.
Inventor： Navin Agarwal , Igor Arsovski , Venkatraghavan Bringivijayaraghavan , Krishnan S. Rengarajan
IPC: G11C11/00 , G11C11/419 , G11C7/10 , G11C7/04 , G11C11/4096 , G11C7/22
CPC classification number: G11C7/22 , G11C7/04 , G11C7/1051 , G11C7/109 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C29/06 , G11C29/12015
Abstract: A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.
Abstract translation: 具有年龄检测和校正（ADAC）电路的存储器件，其检测由偏置温度不稳定性疲劳引起的偏差（即，随时间累积的偏置温度不稳定性应力），并且通过选择性地调整比例（在时间上测量）来计数偏斜， 的活动状态操作到空闲状态操作。 另外，使用类似的ADAC电路的存储器老化装置。
-
公开(公告)号：US09589658B1
公开(公告)日：2017-03-07
申请号：US14828770
申请日：2015-08-18
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Navin Agarwal , Aditya S. Auyisetty , Balaji Jayaraman , Thejas Kempanna , Toshiaki Kirihata , Ramesh Raghavan , Krishnan S. Rengarajan , Rajesh R. Tummuru , Jay M. Shah , Janakiraman Viraraghavan
CPC classification number: G11C16/3427 , G11C7/02 , G11C16/0466 , G11C16/0475 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/28 , G11C17/14 , G11C17/18
Abstract: Approaches for a memory including a cell array are provided. The memory includes a first device of the cell array which is connected to a bitline and a node and controlled by a word line, and a second device of the cell array which comprises a third device which is connected to a source line and the node and controlled by the word line and a fourth device which is connected between the word line and the node. In the memory, in response to another word line in the cell array being activated and the word line not being activated to keep the first device in an unprogrammed state, the third device isolates and floats the node such that a voltage level of a gate to source of the first device is clamped down by the fourth device to a voltage level around zero volts.
Abstract translation: 提供了包括单元阵列的存储器的方法。 存储器包括连接到位线和节点并由字线控制的单元阵列的第一器件和单元阵列的第二器件，其包括连接到源极线和该节点的第三器件，以及 由字线控制，第四器件连接在字线和节点之间。 在存储器中，响应于单元阵列中的另一个字线被激活并且字线未被激活以保持第一器件处于未编程状态，第三器件隔离并漂浮该节点，使得栅极的电压电平 第一器件的源极被第四器件钳位到零电压附近的电压电平。
-
Patent Agency Ranking
公开(公告)号：US20160217832A1
公开(公告)日：2016-07-28
申请号：US14604009
申请日：2015-01-23
Applicant: GLOBALFOUNDRIES INC.
Inventor： Balaji Jayaraman , Thejas Kempanna , Toshiaki Kirihata , Ramesh Raghavan , Krishnan S. Rengarajan , Rajesh R. Tummuru
CPC classification number: G11C7/062 , G11C7/065 , G11C7/08 , G11C11/401 , G11C11/4091 , G11C2211/4013
Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.
Abstract translation: 一种操作双晶体管单比特多时间可编程存储器单元以提供小信号的高增益感测方案的系统和方法。 存储单元包括一对第一晶体管和提供差分信号输出的第二晶体管。 存储单元的第一晶体管耦合具有第一电流源负载晶体管的第一电路支路，而第二晶体管耦合具有第二电流源负载晶体管的第二电路支路。 编程值由第一或第二晶体管之一中的电压阈值偏移来表示。 反馈电路接收差分信号的第一信号或第二信号中的一个，并且响应地产生反馈信号，该反馈信号被同时施加以偏置每个第一和第二电路腿中的每个电流源负载晶体管，以放大 差分信号输出之间的电压差。
-
公开(公告)号：US09460760B2
公开(公告)日：2016-10-04
申请号：US14604009
申请日：2015-01-23
Applicant: GLOBALFOUNDRIES INC.
Inventor： Balaji Jayaraman , Thejas Kempanna , Toshiaki Kirihata , Ramesh Raghavan , Krishnan S. Rengarajan , Rajesh R. Tummuru
CPC classification number: G11C7/062 , G11C7/065 , G11C7/08 , G11C11/401 , G11C11/4091 , G11C2211/4013
Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.
Abstract translation: 一种操作双晶体管单比特多时间可编程存储器单元以提供小信号的高增益感测方案的系统和方法。 存储单元包括一对第一晶体管和提供差分信号输出的第二晶体管。 存储单元的第一晶体管耦合具有第一电流源负载晶体管的第一电路支路，而第二晶体管耦合具有第二电流源负载晶体管的第二电路支路。 编程值由第一或第二晶体管之一中的电压阈值偏移来表示。 反馈电路接收差分信号的第一信号或第二信号中的一个，并且响应地产生反馈信号，该反馈信号被同时施加以偏置每个第一和第二电路腿中的每个电流源负载晶体管，以放大 差分信号输出之间的电压差。
-
公开(公告)号：US10447510B1
公开(公告)日：2019-10-15
申请号：US16266707
申请日：2019-02-04
Applicant: GLOBALFOUNDRIES INC.
Abstract: Disclosed is a power-optimized distributed arithmetic (DA)-based feed forward equalizer (FFE) that performs on-demand equalization processing of a data sample. Specifically, a data stream is represented by digital words, which indicate signal levels at taps on a transmission medium. A screener applies formulas to selected taps as opposed to all taps (e.g., to the main cursor tap, which corresponds to the current data sample, and to specific pre-cursor and post-cursor taps, which correspond to immediately proceeding and following data samples) to determine whether the current data sample (which should indicate a specific two-bit symbol) has degraded during transmission to a point where equalization processing is required. If so, a bypass flag is set to a first level so that the data sample is subjected to equalization processing. If not, the bypass flag is set to a second level so that such processing is bypassed. Also disclosed is a corresponding method.
-
公开(公告)号：US09437282B1
公开(公告)日：2016-09-06
申请号：US14819784
申请日：2015-08-06
Applicant: GLOBALFOUNDRIES Inc.
IPC: G11C7/00 , G11C11/419
CPC classification number: G11C11/419 , G11C7/065
Abstract: A sense amplifier device for sensing a differential signal produced by a memory cell includes a first n-type metal-oxide-semiconductor field-effect transistor (NMOS) stack having multiple NMOS devices sharing a gate connection connected to a complementary data line; and a second NMOS stack having multiple NMOS devices sharing a gate connection connected to a true data line. At least one of the devices in the first stack has higher gate-to-source and drain-to-source voltages than a gate-to-source and drain-to-source voltages of at least one device in the second stack when the voltage of the complementary data line is higher than the true data line. At least one of the devices in the second stack has a higher gate-to-source and drain-to-source voltages than the gate-to-source and drain-to-source voltages of at least one device in the first stack when the voltage of the true data line is higher than the complementary data line.
Abstract translation: 用于感测由存储单元产生的差分信号的读出放大器装置包括：具有多个NMOS器件的第一n型金属氧化物半导体场效应晶体管（NMOS）堆叠，共享连接到互补数据线的栅极连接; 以及具有共享连接到真实数据线的栅极连接的多个NMOS器件的第二NMOS堆叠。 当第一堆叠中的至少一个器件具有比第二堆叠中的至少一个器件的栅极至源极和漏极至源极电压更高的栅极至源极和漏极至源极电压， 的补充数据线高于真实数据线。 第二堆叠中的至少一个器件具有比第一堆叠中的至少一个器件的栅极至源极和漏极至源极电压更高的栅极至源极和漏极至源极电压， 真实数据线的电压高于补充数据线。
-
公开(公告)号：US09286969B2
公开(公告)日：2016-03-15
申请号：US14317806
申请日：2014-06-27
Applicant: GLOBALFOUNDRIES INC.
Inventor： Pankaj Agarwal , Shiju K. Kandiyil , Krishnan S. Rengarajan
IPC: G11C11/00 , G11C11/419
CPC classification number: G11C11/419 , G11C7/065
Abstract: A low power sense amplifier for an SRAM is described. A first pass gate transistor is driven by bit line true and a second pass gate transistor is driven by bit line complement. A first pull down transistor driven by the bit line complement is coupled to the first pass gate transistor, and a second pull down transistor driven by the bit line true is coupled to the second pass gate transistor. A data line true is coupled to a node coupling the first pass gate transistor with the first pull down transistor and a data line complement is coupled to a node coupling the second pass gate transistor with the second pull down transistor. A current cut-off device cuts off parasitic current from flowing through the first pass gate transistor and the first pull down transistor and through the second pass gate transistor and the second pull down transistor.
Abstract translation: 描述了用于SRAM的低功率读出放大器。 第一栅极晶体管由位线为真，第二通道栅极晶体管由位线补码驱动。 由位线补码驱动的第一下拉晶体管耦合到第一栅极晶体管，并且由位线驱动的第二下拉晶体管真实耦合到第二栅极晶体管。 数据线true耦合到将第一通道栅极晶体管与第一下拉晶体管耦合的节点，并且数据线补码耦合到将第二通过栅极晶体管与第二下拉晶体管耦合的节点。 电流截止装置切断寄生电流流过第一栅极晶体管和第一下拉晶体管，并通过第二栅极晶体管和第二下拉晶体管。
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.014 seconds)
