公开(公告)号：US10163558B2

公开(公告)日：2018-12-25

申请号：US15003532

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F5/00 ,  H01F17/00

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly, to structures and methods for implementing high performance vertically stacked inductors and transformers. The structure includes: a first conductor composed of a redistribution line; a second conductor composed of a back end of line wiring layer, coupled to the redistribution line; and a ferro magnetic material between the first conductor and the second conductor.

公开(公告)号：US10784243B2

公开(公告)日：2020-09-22

申请号：US15997277

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkata Narayana Rao Vanukuru

IPC: H01L25/18 ,  H01L27/01 ,  H01L23/00 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniplanar (e.g., single layer) passive circuitry and methods of manufacture. The structure includes: passive circuitry comprising plural components each of which are formed on a same wiring level; and interconnects on the same wiring level connecting the plural components of the passive circuitry.

公开(公告)号：US20190371776A1

公开(公告)日：2019-12-05

申请号：US15997277

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkata Narayana Rao Vanukuru

IPC: H01L25/18 ,  H01L27/01 ,  H01L23/00

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to uniplanar (e.g., single layer) passive circuitry and methods of manufacture. The structure includes: passive circuitry comprising plural components each of which are formed on a same wiring level; and interconnects on the same wiring level connecting the plural components of the passive circuitry.

公开(公告)号：US20170140865A1

公开(公告)日：2017-05-18

申请号：US14942311

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F21/12 ,  H01F41/041 ,  H01F2027/2809

Abstract: This disclosure relates generally to semiconductors, and more particularly, to structures and methods for implementing high performance multi-frequency inductors with airgaps or other low-k dielectric material. The structure includes: a plurality of concentric conductive bands; a low-k dielectric area selectively placed between inner windings of the plurality of concentric conductive bands; and insulator material with a higher-k dielectric material than the low-k dielectric area selectively placed between remaining windings of the plurality of concentric conductive bands.

公开(公告)号：US09966182B2

公开(公告)日：2018-05-08

申请号：US14942311

申请日：2015-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F21/12 ,  H01F41/041 ,  H01F2027/2809

Abstract: This disclosure relates generally to semiconductors, and more particularly, to structures and methods for implementing high performance multi-frequency inductors with airgaps or other low-k dielectric material. The structure includes: a plurality of concentric conductive bands; a low-k dielectric area selectively placed between inner windings of the plurality of concentric conductive bands; and insulator material with a higher-k dielectric material than the low-k dielectric area selectively placed between remaining windings of the plurality of concentric conductive bands.

公开(公告)号：US20170213637A1

公开(公告)日：2017-07-27

申请号：US15003532

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F41/06

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F2017/0066 ,  H01F2027/2809

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly, to structures and methods for implementing high performance vertically stacked inductors and transformers. The structure includes: a first conductor composed of a redistribution line; a second conductor composed of a back end of line wiring layer, coupled to the redistribution line; and a ferro magnetic material between the first conductor and the second conductor.

公开(公告)号：US20170169934A1

公开(公告)日：2017-06-15

申请号：US14969772

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. STAMPER ,  Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F41/04

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to patterned magnetic shields for inductors and methods of manufacture. The structure includes: an inductor structure formed over a wafer; and a patterned magnetic material formed on a plane above, below or above and below the wafer and at a distance away from the inductor structure so as to not decrease inductance of the inductor structure.