公开(公告)号：US20200243439A1

公开(公告)日：2020-07-30

申请号：US16256595

申请日：2019-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. STAMPER ,  Daisy A. VAUGHN ,  Stephen R. BOSLEY ,  Zhong-Xiang HE

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01L23/528 ,  H01G4/08 ,  H01G4/232 ,  H01G4/33

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

公开(公告)号：US20210074730A1

公开(公告)日：2021-03-11

申请号：US16561956

申请日：2019-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. STAMPER ,  Steven M. SHANK ,  Siva P. ADUSUMILLI ,  Michel J. ABOU-KHALIL

IPC: H01L27/12 ,  H01L27/02 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L21/3065 ,  H01L29/40 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.

公开(公告)号：US20180145160A1

公开(公告)日：2018-05-24

申请号：US15360295

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. CAMILLO-CASTILLO ,  Vibhor JAIN ,  Qizhi LIU ,  Anthony K. STAMPER

IPC: H01L29/737 ,  H01L27/082 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8222 ,  H01L29/66 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H03F3/21

CPC classification number: H01L29/7375 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/324 ,  H01L21/8222 ,  H01L27/0823 ,  H01L27/0825 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/7371 ,  H03F3/21 ,  H03F2200/294

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

公开(公告)号：US20180122689A1

公开(公告)日：2018-05-03

申请号：US15856525

申请日：2017-12-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. ADKISSON ,  Anthony K. STAMPER

IPC: H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L21/8249

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/8249 ,  H01L23/485 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact via to a first portion of a first device. The method further includes filling the first contact via with metal material to form a first metal contact to the first portion of the first device. The method further includes forming additional contact vias to other portions of the first device and contacts of a second device. The method further includes cleaning the additional contact vias while protecting the first metal contact of the first portion of the first device. The method further includes filling the additional contact vias with metal material to form additional metal contacts to the other portions of the first device and the second device.

公开(公告)号：US20170169934A1

公开(公告)日：2017-06-15

申请号：US14969772

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. STAMPER ,  Venkata Narayana Rao Vanukuru

IPC: H01F27/28 ,  H01F41/04

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to patterned magnetic shields for inductors and methods of manufacture. The structure includes: an inductor structure formed over a wafer; and a patterned magnetic material formed on a plane above, below or above and below the wafer and at a distance away from the inductor structure so as to not decrease inductance of the inductor structure.

公开(公告)号：US20210134716A1

公开(公告)日：2021-05-06

申请号：US17118876

申请日：2020-12-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. STAMPER ,  Daisy A. VAUGHN ,  Stephen R. BOSLEY ,  Zhong-Xiang HE

IPC: H01L23/522 ,  H01L27/08 ,  H01L49/02 ,  H01G4/33 ,  H01G4/08 ,  H01G4/232 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to tight pitch wirings and capacitors and methods of manufacture. The structure includes: a capacitor including: a bottom plate of a first conductive material; an insulator material on the bottom plate; and a top plate of a second conductive material on the insulator material; and a plurality of wirings on a same level as the bottom plate and composed of the second conductive material.

公开(公告)号：US20210066194A1

公开(公告)日：2021-03-04

申请号：US17097432

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. PEKARIK ,  Anthony K. STAMPER ,  Vibhor JAIN

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/00 ,  H01L23/62

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

公开(公告)号：US20200335612A1

公开(公告)日：2020-10-22

申请号：US16388500

申请日：2019-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC: H01L29/737 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US20200013855A1

公开(公告)日：2020-01-09

申请号：US16575675

申请日：2019-09-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. STAMPER ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US20190312142A1

公开(公告)日：2019-10-10

申请号：US15947364

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. ADUSUMILLI ,  Steven M. SHANK ,  Anthony K. STAMPER ,  John J. ELLIS-MONAGHAN

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L27/12 ,  H01L21/02 ,  H01L23/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.