公开(公告)号：US10685951B1

公开(公告)日：2020-06-16

申请号：US16214450

申请日：2018-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joseph Versaggi

IPC: H01L27/02 ,  H01L27/105 ,  H01L45/00 ,  H01L21/768 ,  H01L43/12 ,  G11C5/06

Abstract: Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.

公开(公告)号：US09564375B2

公开(公告)日：2017-02-07

申请号：US14054040

申请日：2013-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy Mann ,  Sandeep Puri ,  Sonia Ghosh ,  Anuj Gupta ,  Xusheng Wu

IPC: G06F17/50 ,  H01L21/66

CPC classification number: H01L22/14 ,  G01B2210/56 ,  G06F17/5063 ,  G06F17/5068

Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

Abstract translation: 公开了用于提取晶体管沟道宽度的方法和设计结构。 实施例可以包括根据晶体管的拉出沟道宽度确定多个集成电路的晶体管的有效沟道宽度，以及基于有效沟道宽度确定目标晶体管的目标沟道宽度。

公开(公告)号：US10777607B1

公开(公告)日：2020-09-15

申请号：US16389331

申请日：2019-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Anuj Gupta

IPC: H01L27/22 ,  H01L21/768 ,  H01L27/02 ,  H01L27/24 ,  H01L29/78

Abstract: Structures for a bitcell of a non-volatile memory and methods of fabricating such structures. A field-effect transistor of the bitcell includes a gate having gate electrodes that are arranged in a four contacted (poly) pitch layout. An interconnect structure is arranged over the field-effect transistor, and a memory element arranged in the interconnect structure. The memory element is connected by the interconnect structure with the field-effect transistor.

公开(公告)号：US20200185374A1

公开(公告)日：2020-06-11

申请号：US16214450

申请日：2018-12-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joseph Versaggi

IPC: H01L27/02 ,  H01L27/105 ,  G11C5/06 ,  H01L21/768 ,  H01L43/12 ,  H01L45/00

Abstract: Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.