公开(公告)号：US10109599B2

公开(公告)日：2018-10-23

申请号：US15387120

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Cathryn J. Christiansen ,  Anthony K. Stamper ,  Tom C. Lee ,  Ian Mccallum-Cook

IPC: H01L29/45 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

公开(公告)号：US20180174982A1

公开(公告)日：2018-06-21

申请号：US15387120

申请日：2016-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Cathryn J. Christiansen ,  Anthony K. Stamper ,  Tom C. Lee ,  Ian Mccallum-Cook

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L29/45

CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/45

Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.