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    Electrostatic discharge protection circuit with a fail-safe mechanism
    4.
    发明授权
    Electrostatic discharge protection circuit with a fail-safe mechanism 有权
    具有故障安全机构的静电放电保护电路

    公开(公告)号：US09413169B2

    公开(公告)日：2016-08-09

    申请号：US14243295

    申请日：2014-04-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam

    IPC: H02H9/04

    CPC classification number: H02H9/046 ,  H02H9/042

    Abstract: Circuits and methods for providing electrostatic discharge protection. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, a transmission gate configured to selectively connect the node of the timing circuit with the power clamp device, and a control circuit coupled with the node. The control circuit is configured to control the transmission gate based upon whether or not the capacitor is defective. The timing circuit may be deactivated if the capacitor in the timing circuit is defective and the associated chip is powered. Alternatively, the timing circuit may be activated if the capacitor in the timing circuit is not defective.

    Abstract translation: 提供静电放电保护的电路和方法。 保护电路可以包括功率钳位装置，包括电阻器的定时电路和与节点处的电阻器耦合的电容器，被配置为选择性地将定时电路的节点与电源钳位装置连接的传输门，以及 控制电路与节点耦合。 控制电路被配置为基于电容器是否有缺陷来控制传输门。 如果定时电路中的电容器有故障并且相关的芯片被供电，则定时电路可以被去激活。 或者，如果定时电路中的电容器没有故障，则定时电路可以被激活。

    Integrated circuit structure with continuous metal crack stop
    5.
    发明授权
    Integrated circuit structure with continuous metal crack stop 有权

    公开(公告)号：US10109599B2

    公开(公告)日：2018-10-23

    申请号：US15387120

    申请日：2016-12-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Cathryn J. Christiansen ,  Anthony K. Stamper ,  Tom C. Lee ,  Ian Mccallum-Cook

    IPC: H01L29/45 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

    INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP
    6.
    发明申请
    INTEGRATED CIRCUIT STRUCTURE WITH CONTINUOUS METAL CRACK STOP 审中-公开

    公开(公告)号：US20180174982A1

    公开(公告)日：2018-06-21

    申请号：US15387120

    申请日：2016-12-21

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Cathryn J. Christiansen ,  Anthony K. Stamper ,  Tom C. Lee ,  Ian Mccallum-Cook

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L29/45

    CPC classification number: H01L23/562 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/45

    Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.

    ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE
    8.
    发明申请
    ELECTROSTATIC DISCHARGE AND PASSIVE STRUCTURES INTEGRATED IN A VERITCAL GATE FIN-TYPE FIELD EFFECT DIODE 有权
    静电放电和被动结构集成在栅栏栅极型场效应二极管

    公开(公告)号：US20160379972A1

    公开(公告)日：2016-12-29

    申请号：US15140516

    申请日：2016-04-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Robert J. Gauthier, JR. ,  Tom C. Lee ,  You Li ,  Rahul Mishra ,  Souvick Mitra ,  Andreas Scholze

    IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

    CPC classification number: H01L27/0255 ,  H01L27/0266 ,  H01L27/027 ,  H01L27/0288 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42372 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/7855 ,  H01L2029/7858

    Abstract: Field effect diode structures utilize a junction structure that has an L-shape in cross-section (a fin extending from a planar portion). An anode is positioned at the top surface of the fin, and a cathode is positioned at the end surface of the planar portion. The perpendicularity of the fin and the planar portion cause the anode and cathode to be perpendicular to one another. A first gate insulator contacts the fin between the top surface and the planar portion. A first gate conductor contacts the first gate insulator, and the first gate insulator is between the first gate conductor and the surface of the fin. Additionally, a second gate insulator contacts the planar portion between the end surface and the fin. A second gate conductor contacts the second gate insulator, and the second gate insulator is between the second gate conductor and the surface of the planar portion.

    Abstract translation: 场效应二极管结构使用横截面为L形的接合结构（从平面部分延伸的翅片）。 阳极位于翅片的顶面，阴极位于平面部分的端面。 翅片和平面部分的垂直度导致阳极和阴极彼此垂直。 第一栅极绝缘体在顶表面和平面部分之间接触翅片。 第一栅极导体接触第一栅极绝缘体，并且第一栅极绝缘体位于第一栅极导体和鳍的表面之间。 另外，第二栅极绝缘体接触端面和鳍之间的平面部分。 第二栅极导体与第二栅极绝缘体接触，第二栅极绝缘体位于第二栅极导体与平面部分的表面之间。

    Methodology of grading reliability and performance of chips across wafer
    10.
    发明授权
    Methodology of grading reliability and performance of chips across wafer 有权
    晶片上芯片的可靠性和性能分级方法

    公开(公告)号：US09575115B2

    公开(公告)日：2017-02-21

    申请号：US13649699

    申请日：2012-10-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Nathaniel R. Chadwick ,  James P. Di Sarro ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Kirk D. Peterson ,  Andrew A. Turner

    IPC: G01R31/28 ,  H01L21/66

    CPC classification number: G01R31/2872 ,  G01R31/2831 ,  G01R31/2894 ,  H01L22/14 ,  H01L22/20

    Abstract: A system and method sorts integrated circuit devices. Integrated circuit devices are manufactured on a wafer according to an integrated circuit design using manufacturing equipment. The design produces integrated circuit devices that are identically designed and perform differently based on manufacturing process variations. The integrated circuit devices are for use in a range of environmental conditions, when placed in service. Testing is performed on the integrated circuit devices. Environmental maximums are individually predicted for each device. The environmental maximums comprise ones of the environmental conditions that must not be exceeded for each device to perform above a given failure rate. Each integrated circuit device is assigned at least one of a plurality of grades based on the environmental maximums predicted for each device. The integrated circuit devices are provided to different forms of service having different ones of the environmental conditions based on the grades assigned to each device.

    Abstract translation: 一种系统和方法对集成电路器件进行排序。 根据使用制造设备的集成电路设计，在晶片上制造集成电路器件。 该设计生产的集成电路器件根据制造工艺变化相同设计和执行不同。 集成电路设备在使用时可用于一系列环境条件。 在集成电路器件上进行测试。 每个设备单独预测环境最大值。 环境最大值包括每个设备在给定故障率以上执行时不得超过的环境条件。 基于为每个设备预测的环境最大值，为每个集成电路设备分配多个等级中的至少一个。 基于分配给每个设备的等级，将集成电路设备提供给具有不同环境条件的不同服务形式。

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