公开(公告)号：US09602271B2

公开(公告)日：2017-03-21

申请号：US14726945

申请日：2015-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiftach Benjamini ,  Yang Liu ,  Cheng Wei Song ,  Kai Yang

IPC: H04L7/00

CPC classification number: H04L7/0037 ,  H04J3/0667 ,  H04J3/0697 ,  H04L7/0012 ,  H04L7/04 ,  H04L7/08 ,  H04L25/14

Abstract: A method for determining a slave clock to master clock time difference with an alignment marker. The method selects and transmits a first alignment marker at a first time by a transmitter that has a master clock in a first message to a receiver that has a slave clock. Subsequent to transmitting the first message, the method further transmits a second message that contains the first time and an identity of the first alignment marker. The method further receives the first message and records a second time that the first message is received. The method further receives the second message and the first time and the identity of the first alignment marker. The method further determines a transmission delay and generates a time difference from the slave clock to the master clock.

公开(公告)号：US10411832B2

公开(公告)日：2019-09-10

申请号：US15336974

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Yang Liu ,  Jilei Yin ,  Wei Jiang

IPC: H04L1/00

Abstract: Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.

公开(公告)号：US10298345B2

公开(公告)日：2019-05-21

申请号：US15406350

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Bin Sun ,  Yuan Yao ,  Zhen Han

IPC: H04J3/06

Abstract: Aspects of the present disclosure includes a method and program product for clock synchronization of a networked computer system. The method records a time (t1) when a first codeword marker in a datastream is sent from a master computer to a slave computer and records a second time (t2) when the slave computer receives the first codeword marker. The method includes recording a third time (t3) when a third codeword marker in a datastream is sent from the slave computer to the master computer. The method includes recording a fourth time t4 when the master receives the third codeword marker from the slave. The method calculates a time offset θ, according to; θ = ( t ⁢ ⁢ 2 - t ⁢ ⁢ 1 ) + ( t ⁢ ⁢ 4 - t ⁢ ⁢ 3 ) 2 , and a roundtrip delay δ, according to δ=(t4−t1)−(t3−t2). The clock in the slave computer is synchronized with a clock in the master computer using θ and δ.

公开(公告)号：US20180205477A1

公开(公告)日：2018-07-19

申请号：US15406350

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Bin Sun ,  Yuan Yao ,  Zhen Han

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: Aspects of the present disclosure includes a method and program product for clock synchronization of a networked computer system. The method records a time (t1) when a first codeword marker in a datastream is sent from a master computer to a slave computer and records a second time (t2) when the slave computer receives the first codeword marker. The method includes recording a third time (t3) when a third codeword marker in a datastream is sent from the slave computer to the master computer. The method includes recording a fourth time t4 when the master receives the third codeword marker from the slave. The method calculates a time offset θ, according to; θ = ( t   2 - t   1 ) + ( t   4 - t   3 ) 2 , and a roundtrip delay δ, according to δ=(t4−t1)−(t3−t2). The clock in the slave computer is synchronized with a clock in the master computer using θ and δ.

公开(公告)号：US10784976B2

公开(公告)日：2020-09-22

申请号：US16196970

申请日：2018-11-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kai Yang ,  Adrian Butter ,  Bin Sun ,  Yijian Qi ,  Jilei Yin

IPC: H04J3/06

Abstract: A system and apparatus for obtaining clock synchronization of networked devices and related method are provided. Embodiments include a computer-implemented system, including a primary device having a first high accuracy timestamping assist (HATA) unit attached to a first physical layer; a first time stamping unit; a first clock control; a first medium access control layer connected to the first time stamping unit and the first physical layer via a medium independent interface. A secondary device includes a second HATA unit attached to a second physical layer; a second timestamping unit; a second clock control. The first and second HATA units are configured to detect a departure time, an arrival time, or a combination thereof of a first alignment marker over transmitter serializer and receiver deserializer interfaces of a data transmission between the primary device and the secondary device.

公开(公告)号：US10104148B2

公开(公告)日：2018-10-16

申请号：US15397028

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Adrian Butter ,  Bin Sun ,  Bin Yu

IPC: H04L12/40 ,  H04L29/06 ,  H04L1/00 ,  H04L29/08 ,  H04L12/64

Abstract: In methods, systems, and devices, master and slave node timestamp synchronization units identify a node start frame delimiter of a time protocol message on transmission medium by matching patterns in the time protocol message to known start frame delimiter patterns. Master and slave node processors of such timestamp synchronization units capture a corresponding node clock time at which the node start frame delimiter is identified by referring to a corresponding node clock signal while each is identifying the node start frame delimiter. The master and slave node processors perform compensation of the node clock time by making adjustments to the node clock time for known time latency. The master and slave node timestamp synchronization units then output the node clock time as timestamps to corresponding timestamp units.

公开(公告)号：US20180191802A1

公开(公告)日：2018-07-05

申请号：US15397028

申请日：2017-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Adrian Butter ,  Bin Sun ,  Bin Yu

IPC: H04L29/06 ,  H04L1/00

CPC classification number: H04L65/608 ,  H04L1/0018 ,  H04L69/323 ,  H04L2012/6454

Abstract: In methods, systems, and devices, master and slave node timestamp synchronization units identify a node start frame delimiter of a time protocol message on transmission medium by matching patterns in the time protocol message to known start frame delimiter patterns. Master and slave node processors of such timestamp synchronization units capture a corresponding node clock time at which the node start frame delimiter is identified by referring to a corresponding node clock signal while each is identifying the node start frame delimiter. The master and slave node processors perform compensation of the node clock time by making adjustments to the node clock time for known time latency. The master and slave node timestamp synchronization units then output the node clock time as timestamps to corresponding timestamp units.

公开(公告)号：US20180123733A1

公开(公告)日：2018-05-03

申请号：US15336974

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Yang Liu ,  Jilei Yin ,  Wei Jiang

IPC: H04L1/00

CPC classification number: H04L1/0052 ,  H04L1/0043

Abstract: Disclosed are Ethernet physical layer devices (e.g., a transceiver, a receiver and a transmitter) with integrated physical coding and forward error correction sub-layers. Each physical layer device includes a physical coding sub-layer (PCS), a forward error correction sub-layer (FEC) and integration block(s). Each integration block halts, for some number of clock cycles, a data stream in portions of a data path (e.g., portions of a transmitter (TX) data path or portions a receiver (RX) data path) within the PCS and the FEC in order to compensate for processing of that data stream by a data processor (e.g., a code word mark (CWM) inserter or a CWM remover) contained in the portion of the data path within the FEC. Use of such integration block(s) eliminates the need for redundant components in the PCS and FEC, thereby reducing latency, costs and chip area consumption. Also disclosed are associated methods.