公开(公告)号：US20240234305A1

公开(公告)日：2024-07-11

申请号：US18150831

申请日：2023-01-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh M. Pandey ,  Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Chung F. Tan ,  Judson R. Holt

IPC: H01L23/525 ,  H01L23/34 ,  H01L23/62

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L23/62

Abstract: A structure includes: an electrically programmable fuse (e-fuse) including an anode and a cathode; at least one transistor positioned adjacent the e-fuse; and an electrically conductive interconnect coupling the cathode of the e-fuse to the at least one transistor, wherein the at least one transistor includes at least one semiconductor fin extending perpendicularly to the e-fuse.

公开(公告)号：US11450573B2

公开(公告)日：2022-09-20

申请号：US16903559

申请日：2020-06-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： George R. Mulfinger ,  Chung F. Tan ,  Ryan W. Sporer

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/02

Abstract: A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.