公开(公告)号：US11907685B2

公开(公告)日：2024-02-20

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: H04L9/32 ,  G06F7/58 ,  H04L9/08 ,  G06F21/00 ,  G06F21/73 ,  G06F21/72 ,  G06F21/76 ,  H01L21/02 ,  H01L27/088

CPC classification number: G06F7/588 ,  G06F21/00 ,  G06F21/72 ,  G06F21/73 ,  G06F21/76 ,  H01L21/02233 ,  H04L9/0866 ,  H04L9/3278 ,  H01L27/088 ,  H04L2209/12

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US20220285274A1

公开(公告)日：2022-09-08

申请号：US17194565

申请日：2021-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hongru Ren ,  David Pritchard ,  Ryan W. Sporer ,  Manjunatha Prabhu

IPC: H01L23/535 ,  H01L27/12 ,  H01L21/74

Abstract: An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

公开(公告)号：US20220128762A1

公开(公告)日：2022-04-28

申请号：US17082291

申请日：2020-10-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Ryan W. Sporer ,  Karen A. Nummy

IPC: G02B6/122

Abstract: Structures and methods implement an enlarged waveguide. The structure may include a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a semiconductor substrate. An inter-level dielectric (ILD) layer is over the SOI substrate. A first waveguide has a lower surface extending at least partially into the buried insulator layer, which allows vertical enlargement of the waveguide, without increasing the thickness of the ILD layer or increasing the length of interconnects to other devices. The enlarged waveguide may include nitride, and can be implemented with other conventional silicon and nitride waveguides.

公开(公告)号：US20210141610A1

公开(公告)日：2021-05-13

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: G06F7/58 ,  H04L9/32 ,  H01L29/772 ,  H01L27/07 ,  H01L21/8234

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US10943814B1

公开(公告)日：2021-03-09

申请号：US16547474

申请日：2019-08-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ryan W. Sporer ,  Jiehui Shu

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/768 ,  H01L21/74

Abstract: A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.

公开(公告)号：US11610843B2

公开(公告)日：2023-03-21

申请号：US17194565

申请日：2021-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hongru Ren ,  David Pritchard ,  Ryan W. Sporer ,  Manjunatha Prabhu

IPC: H01L23/535 ,  H01L21/74 ,  H01L27/12

Abstract: An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

公开(公告)号：US11450573B2

公开(公告)日：2022-09-20

申请号：US16903559

申请日：2020-06-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： George R. Mulfinger ,  Chung F. Tan ,  Ryan W. Sporer

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L27/12 ,  H01L21/02

Abstract: A structure and method use different stress-inducing isolation dielectrics to induce appropriate stresses in different polarity FETs to improve performance of both type FETs. The structure may include a first stress-inducing isolation dielectric surrounding and contacting a first active region for a p-type field effect transistor (PFET), and a second stress-inducing isolation dielectric surrounding and contacting a second active region for an n-type field effect transistor (NFET). The first and second stress-inducing isolation dielectrics induce different types of stress, thus improving performance of both polarity of FETs.

公开(公告)号：US11409037B2

公开(公告)日：2022-08-09

申请号：US17082291

申请日：2020-10-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Ryan W. Sporer ,  Karen A. Nummy

IPC: G02B6/122 ,  G02B6/12

Abstract: Structures and methods implement an enlarged waveguide. The structure may include a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a semiconductor substrate. An inter-level dielectric (ILD) layer is over the SOI substrate. A first waveguide has a lower surface extending at least partially into the buried insulator layer, which allows vertical enlargement of the waveguide, without increasing the thickness of the ILD layer or increasing the length of interconnects to other devices. The enlarged waveguide may include nitride, and can be implemented with other conventional silicon and nitride waveguides.