公开(公告)号：US20210398875A1

公开(公告)日：2021-12-23

申请号：US17465345

申请日：2021-09-02

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI ,  Peter Anthony DI MASO

IPC: H01L23/367 ,  H01L23/538 ,  H01L29/778 ,  H01L29/20 ,  H01L25/11 ,  H01L23/498

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.

公开(公告)号：US20200185302A1

公开(公告)日：2020-06-11

申请号：US16705696

申请日：2019-12-06

Applicant: GaN Systems Inc.

Inventor： Juncheng LU ,  Di CHEN ,  Larry SPAZIANI ,  Peter Anthony DI MASO

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/498 ,  H01L29/20 ,  H01L25/11 ,  H01L29/778

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses. These pins are configured to provide a low inductance path for high-frequency current and balance inductances of the power commutation loops for each switch.