公开(公告)号：US20250023464A1

公开(公告)日：2025-01-16

申请号：US18350664

申请日：2023-07-11

Applicant: GAN SYSTEMS INC.

Inventor： Krishnaswamy NAGARAJ ,  Nan XING ,  Sridhar RAMASWAMY ,  Edward MACROBBIE ,  Robert Wayne MOUNGER ,  Lucas Andrew MILNER

IPC: H02M3/07

Abstract: A voltage supply circuit that generates a voltage on a voltage supply node. The voltage supply circuit includes an adjustable capacitor, an alternating voltage source, a charge source, and an adjusting circuit. When the alternating voltage on the second capacitor terminal transitions low, the voltage on the first capacitor terminal also becomes low, and the charge source provides charge to the first capacitor terminal of the adjustable capacitor. When the alternating voltage on the second capacitor terminal transitions high, the voltage on the first capacitor terminal also becomes high, and charge is thereby pumped from the first capacitor terminal to the voltage supply node. The adjusting circuit periodically samples the voltage on the voltage supply node, and adjusts the capacitance of the adjustable capacitor to increase or decrease that voltage.

公开(公告)号：US20240364201A1

公开(公告)日：2024-10-31

申请号：US18309651

申请日：2023-04-28

Applicant: GAN SYSTEMS INC.

Inventor： Yalong LI ,  Yinglai XIA ,  Robert Wayne Mounger ,  Nan XING ,  Edward MacRobbie ,  Zhemin ZHANG

IPC: H02M1/00 ,  H02M1/08 ,  H02M3/156

CPC classification number: H02M1/0009 ,  H02M1/08 ,  H02M3/156

Abstract: A circuit that includes a power transistor and at least one sense transistor and that uses the control drive terminal to not only control the power transistor and the sense transistor, but also to provide power to a current sense circuit. The control nodes of the power transistor and sense transistor are connected, and the input nodes of the power transistor and the sense transistor are also connected. The current sense circuit is connected to the sense transistor control node and is configured to detect current passing through the sense transistor. The current sense circuit is also connected to the control drive terminal and is configured to draw power from the control drive terminal when a high control signal is present on the control drive terminal. Accordingly, the current sense circuit does not require an independent fixed high voltage supply in order to operate.

公开(公告)号：US20240283441A1

公开(公告)日：2024-08-22

申请号：US18172922

申请日：2023-02-22

Applicant: GAN SYSTEMS INC.

Inventor： Nan XING ,  Yinglai XIA ,  Yalong LI ,  Zhemin ZHANG

IPC: H03K17/082 ,  H03K5/24

CPC classification number: H03K17/0822 ,  H03K5/24

Abstract: Desaturation protection for a power field-effect transistor. The desaturation protection circuit includes the power field-effect transistor and a sense field-effect transistor that each have threshold voltages that are approximately the same. The sense field-effect transistor shares a gate terminal with the power field-effect transistor and shares a drain terminal with the power field-effect transistor. The circuit also includes a comparator having a first input terminal connected to a source terminal of the sense field-effect transistor, and having a second input terminal connected to a voltage source that is an offset voltage below a supply voltage. The circuit also includes a pull-up network configured to cause the output of the comparator to represent a state of whether the sense field-effect transistor is on or off, and can directly drive the turning off of the power transistor.

公开(公告)号：US20240213127A1

公开(公告)日：2024-06-27

申请号：US18522911

申请日：2023-11-29

Applicant: GAN SYSTEMS INC.

Inventor： Abhinandan DIXIT ,  An-Sheng CHENG ,  Di CHEN ,  Hossein MOUSAVIAN

IPC: H01L23/495 ,  H01L21/8234 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L21/823475 ,  H01L23/49568 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16056 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1033 ,  H01L2924/13064

Abstract: A laminated embedded die package for a power semiconductor device, wherein a laminated body comprises a layup of a plurality of electrically conductive layers and dielectric layers. The die may be mounted in thermal contact with a leadframe. Electrical connections between contact areas of the die, external contact pads of the package and internal conductive layers are made by electrically conductive vias or microvias, formed by laser drilling of vias through the dielectric layers, which are then filled with conductive metal. A plurality of unfilled half-vias are arranged around edges of the laminated body adjacent external contact pads. Half-vias are formed by laser or mechanical drilling along scribe lines before singulation of packages. Surface plating of the half-vias comprises a solder wettable material. The half-vias are unfilled to form a wettable flank which allows for lateral wicking of solder during surface mounting, to facilitate optical inspection of solder reliability.

公开(公告)号：US20240186831A1

公开(公告)日：2024-06-06

申请号：US18494505

申请日：2023-10-25

Applicant: GAN SYSTEMS INC.

Inventor： Tiefeng SHI ,  Paul WIENER

IPC: H02J50/12 ,  H01F38/14

CPC classification number: H02J50/12 ,  H01F38/14

Abstract: High efficiency resonator coils for large gap resonant wireless power transfer (WPT), and a coil design methodology are disclosed. Resonator coils comprise a coil topology defined by coil parameters in which turn dimensions, such as trace widths and spacings of each turn, are configured to reduce or minimize a variance of the z component of magnetic field, over an area of a charging plane at a specified distance, or distance range, from the coil. A Tx resonator coil comprises a capacitor arrangement of tuning and network-matching capacitors for improved coil-to-coil efficiency and end-to-end WPT system performance, e.g. for applications such as through-wall WPT, in the range of tens of watts to at least hundreds of watts. Planar resonator coil topologies are compatible with fabrication using low cost PCB technology, e.g. with multi-layer metal, to reduce losses and improve thermal performance.

公开(公告)号：US20230111992A1

公开(公告)日：2023-04-13

申请号：US17497233

申请日：2021-10-08

Applicant: GaN Systems Inc.

Inventor： Xuechao LIU ,  Di CHEN ,  Yajie QIU

IPC: H02M1/42 ,  H02M3/335

Abstract: An AC/DC Switching Mode Power Supply (SMPS) comprises a PFC stage, an isolated LLC DC/DC converter stage, and a control circuit that provides feedback/control signals to PFC and LLC controllers, to enable a plurality of operating modes, dependent on a sensed peak AC input voltage and required output voltage Vo. The PFC provides a first DC bus voltage Vdc (e.g. 200V) for low line AC input and a second DC bus voltage (e.g. 400V) for high line or universal AC input. A multi-mode LLC converter is operable in a half-bridge mode or a full-bridge mode. For low line AC input, output voltage Vo, and PFC output Vdc, the LLC operates in full-bridge mode; for high line input, output voltage Vo and PFC output 2×Vdc, the LLC operates in half-bridge mode; for universal AC input, output voltage 2×Vo, and PFC output 2×Vdc, the LLC operates in full-bridge mode.

公开(公告)号：US20230080636A1

公开(公告)日：2023-03-16

申请号：US17881096

申请日：2022-08-04

Applicant: GaN Systems Inc.

Inventor： Thomas MACELWEE

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417

Abstract: A semiconductor device structure for a power transistor structure wherein a drain terminal structure comprises field plates to control and reduce the peak intensity of the channel electric field at the drain terminal. By forming multiple field plates with the existing metallization layers, the generation of hot carriers and impact ionization near the drain can be reduced. For example, in a GaN HEMT, this effect is achieved with two field plates that have different capacitive coupling and overlap with the drain ohmic contact to achieve a reduction in the channel electric field. The use of this drain terminal structure may offer a reduction in increase of Rdson with aging that may be observed in devices after high voltage stress.

公开(公告)号：US20220416069A1

公开(公告)日：2022-12-29

申请号：US17358349

申请日：2021-06-25

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Ahmad MIZAN ,  Maryam ABOUIE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L23/00

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in package body comprising dielectric layers and electrically conductive layers, and where an external dielectric coating, such as a solder resist coating is provided on one or both external sides of the package body. The solder resist coating is patterned to avoid inside corners, e.g. the solder resist does not extend around or between electrical contact areas and thermal pads. It is observed that in conventional solder resist coatings, during thermal cycling, cracks tend to initiate at high stress points, such as at sharp inside corners. A solder resist layout which omits inside corners, and comprises outside corners only, is demonstrated to provide significantly improved resistance to initiation and propagation of cracks. Where inside corners are unavoidable, they are appropriately radiused to reduce stress.

公开(公告)号：US20220360259A1

公开(公告)日：2022-11-10

申请号：US17308423

申请日：2021-05-05

Applicant: GaN Systems Inc.

Inventor： Ruoyu HOU ,  Juncheng LU ,  Larry SPAZIANI

IPC: H03K17/0812 ,  H03K17/16

Abstract: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

公开(公告)号：US11431261B2

公开(公告)日：2022-08-30

申请号：US17230390

申请日：2021-04-14

Applicant: GaN Systems Inc.

Inventor： Yajie Qiu ,  Xuechao Liu

IPC: H02M1/36 ,  H02M7/217 ,  H02M1/00 ,  H02J7/02

Abstract: A bulk capacitor circuit for an AC input AC/DC Switching Mode Power Supply, such as an AC/DC adapter/charger without active power factor correction, is provided, comprising a plurality of bulk capacitors having different voltage ratings, and driver and control circuitry comprising AC input voltage sensing and comparator circuitry, which enables selective connection of one or more of the plurality of bulk capacitors, responsive to a sensed AC input voltage range. A startup circuit provides power to the driver circuit initially, so that the AC input voltage can be determined before power-up and enabling of the DC/DC converter. This solution provides for a reduction in capacitor volume, with associated improvement in the power density of an isolated AC/DC power supply, while the startup circuit ensures that an appropriate bulk capacitance is connected at startup for low line AC input, to maintain the ripple voltage in an appropriate range for reliable operation.