公开(公告)号：US12051690B2

公开(公告)日：2024-07-30

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

公开(公告)号：US20240170531A1

公开(公告)日：2024-05-23

申请号：US18056289

申请日：2022-11-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Jie Zeng ,  Souvick Mitra

IPC: H01L29/06 ,  H01L27/02

CPC classification number: H01L29/0623 ,  H01L27/0248

Abstract: The disclosure provides a structure with a buried doped region, and methods to form the same. A structure may include a semiconductor substrate including a first well. A first terminal includes a first doped region in the first well. A second terminal includes a second doped region in the first well. The first well horizontally separates the first doped region from the second doped region. A first buried doped region is in the first well. The first buried doped region overlaps with, and is underneath, the first doped region. The first well vertically separates the first doped region from the first buried doped region.

公开(公告)号：US11776952B1

公开(公告)日：2023-10-03

申请号：US17737272

申请日：2022-05-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Jie Zeng ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

CPC classification number: H01L27/0262 ,  H01L29/66363 ,  H01L29/74

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes first and second wells in the semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite to the first conductivity type. First and second conductor layers are positioned on the semiconductor substrate. The first conductor layer partially overlaps with the first well, and the second conductor layer partially overlaps with the second well. A third doped region, which has the second conductivity type, is laterally positioned in the semiconductor substrate between the first and second conductor layers.

公开(公告)号：US20230141491A1

公开(公告)日：2023-05-11

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.