公开(公告)号：US12051690B2

公开(公告)日：2024-07-30

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

公开(公告)号：US20230343778A1

公开(公告)日：2023-10-26

申请号：US17724548

申请日：2022-04-20

Applicant: GlobalFoundries U.S. Inc.

Inventor： Prantik Mahajan ,  Ajay ,  Vishal Ganesan ,  Ruchil Jain ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Structures for an electrostatic discharge device including a silicon-controlled rectifier and methods of forming a structure for an electrostatic discharge device that includes a silicon-controlled rectifier. The structure includes a first well in a semiconductor substrate, a second well and a third well in the first well, and a fourth well in the first well. The first well has a first conductivity type, and the second well and the third well have the first conductivity type. The fourth well positioned in a lateral direction between the second well and the third well, and the fourth well has a second conductivity type opposite to the first conductivity type. The second well, the third well, and the fourth well are positioned in a vertical direction between the first well and a top surface of the semiconductor substrate.

公开(公告)号：US20240096868A1

公开(公告)日：2024-03-21

申请号：US17946089

申请日：2022-09-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ajay ,  Ruchil Kumar Jain ,  Prantik Mahajan ,  Alban Zaka

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L29/7436

Abstract: Structures for a silicon-controlled rectifier and methods of forming same. The structure comprises a first well, a second well, and a third well in a semiconductor substrate. The third well is positioned between the first well and the second well. A first terminal includes a first doped region in the first well, and a second terminal includes a second doped region in the second well. The first well, the second well, and the second doped region have a first conductivity type, and the third well and the first doped region have a second conductivity type opposite to the first conductivity type. The structure further comprises a third doped region in the third well. The third doped region includes a first segment and a second segment, and the first segment is separated from the second segment by a portion of the first well and a portion of the third well.

公开(公告)号：US20230317835A1

公开(公告)日：2023-10-05

申请号：US17713277

申请日：2022-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Prantik Mahajan

IPC: H01L29/735 ,  H01L29/08 ,  H01L27/02 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L27/0248 ,  H01L29/1008 ,  H01L29/0821 ,  H01L29/0649

Abstract: Disclosed semiconductor structure embodiments include a bipolar junction device configured to have a high holding voltage. The device includes base, collector and emitter terminals. The high holding voltage is achieved because of a uniquely configured emitter terminal. Specifically, the device includes a base well region, which has a first-type conductivity. The emitter terminal includes, adjacent to the base well region (e.g., within and/or on the base well region), an emitter contact region, which has a second-type conductivity, and an ancillary emitter region, which abuts the emitter contact region and which has the first-type conductivity at a higher conductivity level than the base well region. Embodiments vary with regard to the shapes of the emitter contact region and ancillary emitter region. Embodiments also vary with regard to the structures used to isolate the collector terminal from the emitter terminal and with regard to the areas covered by silicide layers.

公开(公告)号：US12068401B2

公开(公告)日：2024-08-20

申请号：US17713277

申请日：2022-04-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Prantik Mahajan

IPC: H01L29/735 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L27/0248 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008

Abstract: Disclosed semiconductor structure embodiments include a bipolar junction device configured to have a high holding voltage. The device includes base, collector and emitter terminals. The high holding voltage is achieved because of a uniquely configured emitter terminal. Specifically, the device includes a base well region, which has a first-type conductivity. The emitter terminal includes, adjacent to the base well region (e.g., within and/or on the base well region), an emitter contact region, which has a second-type conductivity, and an ancillary emitter region, which abuts the emitter contact region and which has the first-type conductivity at a higher conductivity level than the base well region. Embodiments vary with regard to the shapes of the emitter contact region and ancillary emitter region. Embodiments also vary with regard to the structures used to isolate the collector terminal from the emitter terminal and with regard to the areas covered by silicide layers.

公开(公告)号：US20240014204A1

公开(公告)日：2024-01-11

申请号：US17857439

申请日：2022-07-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vishal Ganesan ,  Prantik Mahajan ,  Nandha Kumar Subramani ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well, the second well and the first doped region have a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type. The structure further comprises a deep well in the semiconductor substrate. The deep well has the second conductivity type, the first well is positioned in a vertical direction between the deep well and the top surface of the semiconductor substrate, and the second well is positioned in the vertical direction between the deep well and the top surface of the semiconductor substrate.

公开(公告)号：US20240079482A1

公开(公告)日：2024-03-07

申请号：US17901015

申请日：2022-09-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Prantik Mahajan ,  . Ajay ,  Souvick Mitra ,  Robert J. Gauthier

IPC: H01L29/74 ,  H01L29/06

CPC classification number: H01L29/7432 ,  H01L29/0692 ,  H01L29/742 ,  H01L29/7436 ,  H01L29/0653

Abstract: Device structures including a silicon-controlled rectifier and methods of forming a device structure including a silicon-controlled rectifier. The device structure comprises a first well and a second well in a semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite from the first conductivity type. The second well adjoins the first well along an interface. A third doped region includes a first portion in the first well and a second portion in the second well, and a gate structure that overlaps with a portion of the second well.

公开(公告)号：US20230141491A1

公开(公告)日：2023-05-11

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.