公开(公告)号：US20240304258A1

公开(公告)日：2024-09-12

申请号：US18178926

申请日：2023-03-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramesh Raghavan ,  Chandrahasa Reddy Dinnipati ,  Philipp Bernhard Mosch

IPC: G11C16/26 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/34

Abstract: Embodiments of the disclosure provide a memory assembly with body biasing and related methods to operate such a structure. A structure according to the disclosure includes a memory cell having a pair of memory transistors each having a gate coupled to a word line. A pair of diode-connected transistors each have a source/drain (S/D) terminal coupled to a respective S/D terminal of one of the pair of memory transistors through a multiplexer. A bias voltage source is coupled to each body of the pair of diode-connected transistors or each body of the pair of memory transistors. The bias voltage source applies a different bias voltage to each body of the pair of diode-connected transistors or each body of the pair of memory transistors.