公开(公告)号：US20240363180A1

公开(公告)日：2024-10-31

申请号：US18768518

申请日：2024-07-10

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI ,  Jong Woo KIM

IPC分类号： G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

CPC分类号： G11C16/3459 ,  G11C7/1039 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3404

摘要： A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

公开(公告)号：US20240355397A1

公开(公告)日：2024-10-24

申请号：US18762228

申请日：2024-07-02

申请人： Micron Technology, Inc.

发明人： Vivek Venkata Kalluru ,  Michele Piccardi ,  Taehyun Kim ,  Theodore T. Pekny

IPC分类号： G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C16/3459

摘要： Control logic in a memory device initiates a read operation on a memory array of the memory device and performs a calibration operation to detect a change in string resistance in the memory array. The control logic determines whether the change in string resistance is attributable to charge loss in the memory array, and responsive to determining that the change in string resistance is attributable to charge loss in the memory array, preforms the read operation using calibrated read voltage levels to read data from the memory array.

公开(公告)号：US12125543B2

公开(公告)日：2024-10-22

申请号：US18073276

申请日：2022-12-01

申请人： SK hynix Inc.

发明人： Eun Woo Jo ,  Jong Woo Kim

IPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C16/08 ,  G11C16/3459 ,  G11C16/0483

摘要： A semiconductor memory device includes a memory cell array including memory cells, a peripheral circuit performing a read/verify operation of selected memory cells, and a control logic circuit controlling the read/verify operation of the peripheral circuit. The control logic circuit controls the peripheral circuit to apply a first voltage to a selected word line connected to the selected memory cells, float unselected word lines adjacent to the selected word line among unselected word lines, apply a first under-drive voltage lower than the first voltage to the selected word line during at least a partial period in which the unselected word lines adjacent to the selected word line are floated, and apply a second voltage higher than the first under-drive voltage and lower than the first voltage to the selected word line.

公开(公告)号：US12125533B2

公开(公告)日：2024-10-22

申请号：US17812122

申请日：2022-07-12

申请人： STMicroelectronics (Rousset) SAS ,  STMicroelectronics International N.V.

发明人： Francesco La Rosa ,  Marco Bildgen

IPC分类号： G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

CPC分类号： G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

摘要： In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

公开(公告)号：US12119068B2

公开(公告)日：2024-10-15

申请号：US17675241

申请日：2022-02-18

申请人： Micron Technology, Inc.

发明人： Gary F. Besinga ,  Vamsi Pavan Rayaprolu ,  Steven Michael Kientz ,  Renato C. Padilla

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/3459 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3404

摘要： A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including detecting a power up event of the memory device, responsive to detecting the power up event, selecting an open block of the memory device, wherein the open block comprises a set of pages, determining, based at least in part on an analysis of the set of pages, whether the open block is valid for programming, and responsive to determining that the open block is valid for programming, keeping the open block open for programming.

公开(公告)号：US12119064B2

公开(公告)日：2024-10-15

申请号：US17114475

申请日：2020-12-07

申请人： Intel Corporation

发明人： Pawel Tomkiewicz ,  Jacek Jaworski

IPC分类号： G11C11/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42 ,  G11C29/44

CPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42 ,  G11C29/44

摘要： A memory device including a memory array comprising a plurality of memory cells, respective memory cells each comprising a storage element comprising phase change memory programmable to three unique states; and a controller comprising circuitry, the controller to convert binary data into ternary data at a ratio of three bits of binary data to two trits of ternary data and provide the ternary data to the memory array for storage.

公开(公告)号：US20240339162A1

公开(公告)日：2024-10-10

申请号：US18744776

申请日：2024-06-17

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Po-Hao TSENG

IPC分类号： G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC分类号： G11C16/3404 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

摘要： An encoding method is provided for a memory device which includes an in-memory search (IMS) array having several memory units. The memory units in a same horizontal row are coupled to a first driving circuit through corresponding word lines and coupled to a sensing circuit through a match signal line. Every 2N adjacent memory units in the same horizontal row are arranged as a memory cell. An original data of M-bits is encoded to an encoded data of 2N-bits with a first encoded area including the first to N-th bits of the encoded data and a second encoded area including the (N+1)-th to 2N-th bits of the encoded data. The M bits of the original data have an equivalent binary value increased by an incremental step which is P times of an incremental step for the N bits of the first encoded area.

公开(公告)号：US12112810B2

公开(公告)日：2024-10-08

申请号：US18296430

申请日：2023-04-06

申请人： Kioxia Corporation

发明人： Naoki Matsunaga

IPC分类号： G11C7/00 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52

CPC分类号： G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3404 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/52

摘要： According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

公开(公告)号：US12112808B2

公开(公告)日：2024-10-08

申请号：US18179372

申请日：2023-03-07

申请人： PHISON ELECTRONICS CORP.

发明人： Szu-Wei Chen ,  An-Cin Li ,  Yu-Hung Lin ,  Kai-Wei Tsou

IPC分类号： G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16 ,  G06F13/28 ,  G11C16/04 ,  G11C16/26

CPC分类号： G11C16/26 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/1068 ,  G11C16/0483

摘要： A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.

公开(公告)号：US12112799B2

公开(公告)日：2024-10-08

申请号：US17187526

申请日：2021-02-26

申请人： SK hynix Inc.

发明人： Yong Han

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C2216/14

摘要： An electronic device includes memory devices, and a memory controller configured to provide program commands instructing to store data in the memory devices, each of the memory devices including a memory block including a plurality of memory cells, a peripheral circuit configured to perform a first program operation and a second program operation of storing the data in select memory cells which are memory cells selected from among the plurality of memory cells, in response to the program command, and a program operation controller configured to control the first program operation and the second program operation, the first program operation performed using one logical page data among page data to be stored in the select memory cells, and the second program operation performed using remaining logical page data except for the one logical page data among the page data.