公开(公告)号：US20230056457A1

公开(公告)日：2023-02-23

申请号：US17445461

申请日：2021-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bipul C. Paul ,  Shashank S. Nemawarkar

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

公开(公告)号：US20250098177A1

公开(公告)日：2025-03-20

申请号：US18470314

申请日：2023-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Shashank S. Nemawarkar ,  Bipul C. Paul

IPC: H10B61/00 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/56

Abstract: A disclosed non-volatile memory (NVM) structure is implemented in a fully depleted semiconductor-on-insulator technology processing platform and includes multiple NVM banks with NVM cells including transistors. NVM banks have well regions in a substrate. Transistors of NVM cells of each NVM bank are on an insulator layer above a corresponding well region for that bank. A bias control circuit causes well regions for NVM banks in a standby state to be biased with a reverse back biasing voltage and causes a well region for an NVM bank in an operational state to be biased with a forward back biasing voltage. The bias control circuit can initiate forward back biasing during a cache data retrieval process (before NVM bank access) to ensure that the corresponding well region of an NVM bank at issue is fully biased when, following the cache data retrieval process, access to the NVM bank is still required.

公开(公告)号：US11587601B1

公开(公告)日：2023-02-21

申请号：US17445461

申请日：2021-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bipul C. Paul ,  Shashank S. Nemawarkar

IPC: G11C7/22 ,  G11C7/10

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.