公开(公告)号：US11721621B2

公开(公告)日：2023-08-08

申请号：US17527606

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shweta Vasant Khokale ,  Kaustubh Shanbhag ,  Tamilmani Ethirajan

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/84 ,  H01L23/528

CPC classification number: H01L23/5225 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/1203

Abstract: Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.

公开(公告)号：US20230154844A1

公开(公告)日：2023-05-18

申请号：US17527606

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shweta Vasant Khokale ,  Kaustubh Shanbhag ,  Tamilmani Ethirajan

IPC: H01L23/522 ,  H01L27/12 ,  H01L23/528 ,  H01L21/84

CPC classification number: H01L23/5225 ,  H01L27/1203 ,  H01L23/5226 ,  H01L23/5286 ,  H01L21/84

Abstract: Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.