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    ARCHITECTURE FOR HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING
    2.
    发明申请
    ARCHITECTURE FOR HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING 有权
    高性能，高能效，可编程图像处理的架构

    公开(公告)号：US20160314555A1

    公开(公告)日：2016-10-27

    申请号：US14694828

    申请日：2015-04-23

    Applicant: Google Inc.

    Inventor： Qiuling Zhu ,  Ofer Shacham ,  Albert Meixner ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  David Patterson ,  Neeti Desai ,  Donald Stark ,  Edward T. Chang ,  William R. Mark

    IPC: G06T1/20 ,  G06T1/60 ,  H04N5/91 ,  H04N5/378

    CPC classification number: G06T1/20 ,  G06T1/60 ,  H04N5/378 ,  H04N5/91

    Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.

    Abstract translation: 描述了一种装置。 该装置包括图像处理单元。 图像处理单元包括网络。 图像处理单元包括多个模板处理器电路，每个模板处理器电路各自包括耦合到二维移位寄存器阵列结构的执行单元通道的阵列，以通过执行程序代码来同时处理多个重叠模版。 图像处理单元包括分别耦合在多个模板处理器和网络之间的多个片材生成器。 片材生成器将图像数据的输入线组分解成图像数据的输入片以供模板处理器处理，并且从从模版处理器接收的图像数据的输出片材中形成图像数据的输出线组。 图像处理单元包括耦合到网络的多个行缓冲单元，以在从生成模板处理器到消耗模板处理器的方向上传递线组，以实现整个程序流程。

    Clock period randomization for defense against cryptographic attacks
    6.
    发明授权
    Clock period randomization for defense against cryptographic attacks 有权

    公开(公告)号：US10958414B2

    公开(公告)日：2021-03-23

    申请号：US15436489

    申请日：2017-02-17

    Applicant: GOOGLE INC.

    Inventor： Donald Stark

    IPC: H04L9/00 ,  G06F7/58

    Abstract: Methods, systems, and apparatuses for defending against cryptographic attacks using clock period randomization. The methods, systems, and apparatuses are designed to make side channel attacks and fault injection attacks more difficult by using a clock with a variable period during a cryptographic operation. In an example embodiment, a clock period randomizer includes a fixed delay generator and a variable delay generator, wherein a variable delay generated by the variable delay generator is based on a random or pseudorandom value that is changed occasionally or periodically. The methods, systems, and apparatuses are useful in hardware security applications where fault injection and/or side channel attacks are of concern.

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